369 lines
9.4 KiB
C
369 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2005-2017 Andes Technology Corporation
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#include <linux/cpu.h>
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#include <linux/bootmem.h>
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#include <linux/seq_file.h>
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#include <linux/memblock.h>
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#include <linux/console.h>
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#include <linux/screen_info.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <asm/setup.h>
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#include <asm/sections.h>
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#include <asm/proc-fns.h>
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#include <asm/cache_info.h>
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#include <asm/elf.h>
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#include <nds32_intrinsic.h>
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#define HWCAP_MFUSR_PC 0x000001
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#define HWCAP_EXT 0x000002
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#define HWCAP_EXT2 0x000004
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#define HWCAP_FPU 0x000008
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#define HWCAP_AUDIO 0x000010
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#define HWCAP_BASE16 0x000020
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#define HWCAP_STRING 0x000040
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#define HWCAP_REDUCED_REGS 0x000080
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#define HWCAP_VIDEO 0x000100
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#define HWCAP_ENCRYPT 0x000200
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#define HWCAP_EDM 0x000400
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#define HWCAP_LMDMA 0x000800
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#define HWCAP_PFM 0x001000
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#define HWCAP_HSMP 0x002000
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#define HWCAP_TRACE 0x004000
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#define HWCAP_DIV 0x008000
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#define HWCAP_MAC 0x010000
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#define HWCAP_L2C 0x020000
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#define HWCAP_FPU_DP 0x040000
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#define HWCAP_V2 0x080000
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#define HWCAP_DX_REGS 0x100000
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unsigned long cpu_id, cpu_rev, cpu_cfgid;
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char cpu_series;
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char *endianness = NULL;
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unsigned int __atags_pointer __initdata;
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unsigned int elf_hwcap;
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EXPORT_SYMBOL(elf_hwcap);
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/*
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* The following string table, must sync with HWCAP_xx bitmask,
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* which is defined in <asm/procinfo.h>
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*/
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static const char *hwcap_str[] = {
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"mfusr_pc",
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"perf1",
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"perf2",
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"fpu",
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"audio",
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"16b",
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"string",
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"reduced_regs",
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"video",
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"encrypt",
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"edm",
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"lmdma",
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"pfm",
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"hsmp",
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"trace",
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"div",
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"mac",
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"l2c",
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"fpu_dp",
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"v2",
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"dx_regs",
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NULL,
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};
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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#define WRITE_METHOD "write through"
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#else
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#define WRITE_METHOD "write back"
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#endif
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struct cache_info L1_cache_info[2];
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static void __init dump_cpu_info(int cpu)
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{
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int i, p = 0;
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char str[sizeof(hwcap_str) + 16];
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for (i = 0; hwcap_str[i]; i++) {
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if (elf_hwcap & (1 << i)) {
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sprintf(str + p, "%s ", hwcap_str[i]);
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p += strlen(hwcap_str[i]) + 1;
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}
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}
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pr_info("CPU%d Features: %s\n", cpu, str);
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L1_cache_info[ICACHE].ways = CACHE_WAY(ICACHE);
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L1_cache_info[ICACHE].line_size = CACHE_LINE_SIZE(ICACHE);
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L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE);
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L1_cache_info[ICACHE].size =
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L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].line_size *
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L1_cache_info[ICACHE].sets / 1024;
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pr_info("L1I:%dKB/%dS/%dW/%dB\n", L1_cache_info[ICACHE].size,
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L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways,
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L1_cache_info[ICACHE].line_size);
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L1_cache_info[DCACHE].ways = CACHE_WAY(DCACHE);
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L1_cache_info[DCACHE].line_size = CACHE_LINE_SIZE(DCACHE);
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L1_cache_info[DCACHE].sets = CACHE_SET(DCACHE);
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L1_cache_info[DCACHE].size =
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L1_cache_info[DCACHE].ways * L1_cache_info[DCACHE].line_size *
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L1_cache_info[DCACHE].sets / 1024;
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pr_info("L1D:%dKB/%dS/%dW/%dB\n", L1_cache_info[DCACHE].size,
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L1_cache_info[DCACHE].sets, L1_cache_info[DCACHE].ways,
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L1_cache_info[DCACHE].line_size);
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pr_info("L1 D-Cache is %s\n", WRITE_METHOD);
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if (L1_cache_info[DCACHE].size != L1_CACHE_BYTES)
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pr_crit
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("The cache line size(%d) of this processor is not the same as L1_CACHE_BYTES(%d).\n",
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L1_cache_info[DCACHE].size, L1_CACHE_BYTES);
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#ifdef CONFIG_CPU_CACHE_ALIASING
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{
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int aliasing_num;
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aliasing_num =
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L1_cache_info[ICACHE].size * 1024 / PAGE_SIZE /
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L1_cache_info[ICACHE].ways;
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L1_cache_info[ICACHE].aliasing_num = aliasing_num;
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L1_cache_info[ICACHE].aliasing_mask =
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(aliasing_num - 1) << PAGE_SHIFT;
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aliasing_num =
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L1_cache_info[DCACHE].size * 1024 / PAGE_SIZE /
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L1_cache_info[DCACHE].ways;
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L1_cache_info[DCACHE].aliasing_num = aliasing_num;
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L1_cache_info[DCACHE].aliasing_mask =
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(aliasing_num - 1) << PAGE_SHIFT;
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}
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#endif
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}
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static void __init setup_cpuinfo(void)
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{
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unsigned long tmp = 0, cpu_name;
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cpu_dcache_inval_all();
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cpu_icache_inval_all();
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__nds32__isb();
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cpu_id = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCPUID) >> CPU_VER_offCPUID;
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cpu_name = ((cpu_id) & 0xf0) >> 4;
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cpu_series = cpu_name ? cpu_name - 10 + 'A' : 'N';
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cpu_id = cpu_id & 0xf;
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cpu_rev = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskREV) >> CPU_VER_offREV;
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cpu_cfgid = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCFGID) >> CPU_VER_offCFGID;
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pr_info("CPU:%c%ld, CPU_VER 0x%08x(id %lu, rev %lu, cfg %lu)\n",
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cpu_series, cpu_id, __nds32__mfsr(NDS32_SR_CPU_VER), cpu_id, cpu_rev, cpu_cfgid);
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elf_hwcap |= HWCAP_MFUSR_PC;
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if (((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskBASEV) >> MSC_CFG_offBASEV) == 0) {
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskDIV)
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elf_hwcap |= HWCAP_DIV;
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if ((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskMAC)
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|| (cpu_id == 12 && cpu_rev < 4))
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elf_hwcap |= HWCAP_MAC;
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} else {
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elf_hwcap |= HWCAP_V2;
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elf_hwcap |= HWCAP_DIV;
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elf_hwcap |= HWCAP_MAC;
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}
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if (cpu_cfgid & 0x0001)
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elf_hwcap |= HWCAP_EXT;
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if (cpu_cfgid & 0x0002)
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elf_hwcap |= HWCAP_BASE16;
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if (cpu_cfgid & 0x0004)
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elf_hwcap |= HWCAP_EXT2;
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if (cpu_cfgid & 0x0008)
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elf_hwcap |= HWCAP_FPU;
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if (cpu_cfgid & 0x0010)
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elf_hwcap |= HWCAP_STRING;
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if (__nds32__mfsr(NDS32_SR_MMU_CFG) & MMU_CFG_mskDE)
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endianness = "MSB";
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else
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endianness = "LSB";
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskEDM)
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elf_hwcap |= HWCAP_EDM;
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskLMDMA)
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elf_hwcap |= HWCAP_LMDMA;
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskPFM)
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elf_hwcap |= HWCAP_PFM;
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskHSMP)
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elf_hwcap |= HWCAP_HSMP;
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskTRACE)
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elf_hwcap |= HWCAP_TRACE;
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskAUDIO)
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elf_hwcap |= HWCAP_AUDIO;
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C)
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elf_hwcap |= HWCAP_L2C;
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tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL);
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if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE))
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tmp |= CACHE_CTL_mskDC_EN;
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if (!IS_ENABLED(CONFIG_CPU_ICACHE_DISABLE))
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tmp |= CACHE_CTL_mskIC_EN;
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__nds32__mtsr_isb(tmp, NDS32_SR_CACHE_CTL);
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dump_cpu_info(smp_processor_id());
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}
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static void __init setup_memory(void)
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{
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unsigned long ram_start_pfn;
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unsigned long free_ram_start_pfn;
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phys_addr_t memory_start, memory_end;
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struct memblock_region *region;
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memory_end = memory_start = 0;
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/* Find main memory where is the kernel */
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for_each_memblock(memory, region) {
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memory_start = region->base;
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memory_end = region->base + region->size;
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pr_info("%s: Memory: 0x%x-0x%x\n", __func__,
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memory_start, memory_end);
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}
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if (!memory_end) {
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panic("No memory!");
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}
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ram_start_pfn = PFN_UP(memblock_start_of_DRAM());
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/* free_ram_start_pfn is first page after kernel */
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free_ram_start_pfn = PFN_UP(__pa(&_end));
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max_pfn = PFN_DOWN(memblock_end_of_DRAM());
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/* it could update max_pfn */
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if (max_pfn - ram_start_pfn <= MAXMEM_PFN)
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max_low_pfn = max_pfn;
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else {
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max_low_pfn = MAXMEM_PFN + ram_start_pfn;
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if (!IS_ENABLED(CONFIG_HIGHMEM))
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max_pfn = MAXMEM_PFN + ram_start_pfn;
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}
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/* high_memory is related with VMALLOC */
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high_memory = (void *)__va(max_low_pfn * PAGE_SIZE);
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min_low_pfn = free_ram_start_pfn;
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/*
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* initialize the boot-time allocator (with low memory only).
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*
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* This makes the memory from the end of the kernel to the end of
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* RAM usable.
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*/
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memblock_set_bottom_up(true);
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memblock_reserve(PFN_PHYS(ram_start_pfn), PFN_PHYS(free_ram_start_pfn - ram_start_pfn));
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early_init_fdt_reserve_self();
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early_init_fdt_scan_reserved_mem();
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memblock_dump_all();
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}
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void __init setup_arch(char **cmdline_p)
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{
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early_init_devtree(__atags_pointer ? \
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phys_to_virt(__atags_pointer) : __dtb_start);
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setup_cpuinfo();
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init_mm.start_code = (unsigned long)&_stext;
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init_mm.end_code = (unsigned long)&_etext;
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init_mm.end_data = (unsigned long)&_edata;
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init_mm.brk = (unsigned long)&_end;
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/* setup bootmem allocator */
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setup_memory();
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/* paging_init() sets up the MMU and marks all pages as reserved */
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paging_init();
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/* invalidate all TLB entries because the new mapping is created */
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__nds32__tlbop_flua();
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/* use generic way to parse */
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parse_early_param();
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unflatten_and_copy_device_tree();
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if(IS_ENABLED(CONFIG_VT)) {
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if(IS_ENABLED(CONFIG_DUMMY_CONSOLE))
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conswitchp = &dummy_con;
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}
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*cmdline_p = boot_command_line;
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early_trap_init();
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}
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static int c_show(struct seq_file *m, void *v)
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{
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int i;
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seq_printf(m, "Processor\t: %c%ld (id %lu, rev %lu, cfg %lu)\n",
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cpu_series, cpu_id, cpu_id, cpu_rev, cpu_cfgid);
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seq_printf(m, "L1I\t\t: %luKB/%luS/%luW/%luB\n",
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CACHE_SET(ICACHE) * CACHE_WAY(ICACHE) *
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CACHE_LINE_SIZE(ICACHE) / 1024, CACHE_SET(ICACHE),
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CACHE_WAY(ICACHE), CACHE_LINE_SIZE(ICACHE));
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seq_printf(m, "L1D\t\t: %luKB/%luS/%luW/%luB\n",
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CACHE_SET(DCACHE) * CACHE_WAY(DCACHE) *
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CACHE_LINE_SIZE(DCACHE) / 1024, CACHE_SET(DCACHE),
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CACHE_WAY(DCACHE), CACHE_LINE_SIZE(DCACHE));
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seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
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loops_per_jiffy / (500000 / HZ),
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(loops_per_jiffy / (5000 / HZ)) % 100);
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/* dump out the processor features */
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seq_puts(m, "Features\t: ");
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for (i = 0; hwcap_str[i]; i++)
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if (elf_hwcap & (1 << i))
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seq_printf(m, "%s ", hwcap_str[i]);
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seq_puts(m, "\n\n");
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return 0;
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}
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static void *c_start(struct seq_file *m, loff_t * pos)
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{
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return *pos < 1 ? (void *)1 : NULL;
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}
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static void *c_next(struct seq_file *m, void *v, loff_t * pos)
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{
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++*pos;
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return NULL;
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}
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static void c_stop(struct seq_file *m, void *v)
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{
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}
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struct seq_operations cpuinfo_op = {
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.start = c_start,
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.next = c_next,
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.stop = c_stop,
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.show = c_show
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};
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