272 lines
6.5 KiB
C
272 lines
6.5 KiB
C
/*
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* pata_cmd640.c - CMD640 PCI PATA for new ATA layer
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* (C) 2007 Red Hat Inc
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*
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* Based upon
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* linux/drivers/ide/pci/cmd640.c Version 1.02 Sep 01, 1996
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*
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* Copyright (C) 1995-1996 Linus Torvalds & authors (see driver)
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*
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* This drives only the PCI version of the controller. If you have a
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* VLB one then we have enough docs to support it but you can write
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* your own code.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/gfp.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_cmd640"
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#define DRV_VERSION "0.0.5"
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struct cmd640_reg {
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int last;
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u8 reg58[ATA_MAX_DEVICES];
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};
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enum {
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CFR = 0x50,
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CNTRL = 0x51,
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CMDTIM = 0x52,
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ARTIM0 = 0x53,
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DRWTIM0 = 0x54,
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ARTIM23 = 0x57,
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DRWTIM23 = 0x58,
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BRST = 0x59
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};
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/**
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* cmd640_set_piomode - set initial PIO mode data
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* @ap: ATA port
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* @adev: ATA device
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*
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* Called to do the PIO mode setup.
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*/
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static void cmd640_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct cmd640_reg *timing = ap->private_data;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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struct ata_timing t;
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const unsigned long T = 1000000 / 33;
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const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
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u8 reg;
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int arttim = ARTIM0 + 2 * adev->devno;
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struct ata_device *pair = ata_dev_pair(adev);
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if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) {
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printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
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return;
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}
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/* The second channel has shared timings and the setup timing is
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messy to switch to merge it for worst case */
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if (ap->port_no && pair) {
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struct ata_timing p;
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ata_timing_compute(pair, pair->pio_mode, &p, T, 1);
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ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP);
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}
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/* Make the timings fit */
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if (t.recover > 16) {
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t.active += t.recover - 16;
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t.recover = 16;
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}
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if (t.active > 16)
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t.active = 16;
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/* Now convert the clocks into values we can actually stuff into
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the chip */
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if (t.recover > 1)
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t.recover--; /* 640B only */
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else
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t.recover = 15;
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if (t.setup > 4)
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t.setup = 0xC0;
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else
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t.setup = setup_data[t.setup];
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if (ap->port_no == 0) {
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t.active &= 0x0F; /* 0 = 16 */
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/* Load setup timing */
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pci_read_config_byte(pdev, arttim, ®);
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reg &= 0x3F;
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reg |= t.setup;
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pci_write_config_byte(pdev, arttim, reg);
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/* Load active/recovery */
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pci_write_config_byte(pdev, arttim + 1, (t.active << 4) | t.recover);
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} else {
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/* Save the shared timings for channel, they will be loaded
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by qc_issue. Reloading the setup time is expensive so we
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keep a merged one loaded */
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pci_read_config_byte(pdev, ARTIM23, ®);
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reg &= 0x3F;
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reg |= t.setup;
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pci_write_config_byte(pdev, ARTIM23, reg);
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timing->reg58[adev->devno] = (t.active << 4) | t.recover;
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}
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}
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/**
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* cmd640_qc_issue - command preparation hook
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* @qc: Command to be issued
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*
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* Channel 1 has shared timings. We must reprogram the
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* clock each drive 2/3 switch we do.
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*/
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static unsigned int cmd640_qc_issue(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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struct cmd640_reg *timing = ap->private_data;
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if (ap->port_no != 0 && adev->devno != timing->last) {
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pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]);
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timing->last = adev->devno;
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}
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return ata_sff_qc_issue(qc);
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}
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/**
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* cmd640_port_start - port setup
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* @ap: ATA port being set up
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*
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* The CMD640 needs to maintain private data structures so we
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* allocate space here.
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*/
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static int cmd640_port_start(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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struct cmd640_reg *timing;
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timing = devm_kzalloc(&pdev->dev, sizeof(struct cmd640_reg), GFP_KERNEL);
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if (timing == NULL)
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return -ENOMEM;
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timing->last = -1; /* Force a load */
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ap->private_data = timing;
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return 0;
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}
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static bool cmd640_sff_irq_check(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int irq_reg = ap->port_no ? ARTIM23 : CFR;
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u8 irq_stat, irq_mask = ap->port_no ? 0x10 : 0x04;
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pci_read_config_byte(pdev, irq_reg, &irq_stat);
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return irq_stat & irq_mask;
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}
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static struct scsi_host_template cmd640_sht = {
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ATA_PIO_SHT(DRV_NAME),
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};
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static struct ata_port_operations cmd640_port_ops = {
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.inherits = &ata_sff_port_ops,
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/* In theory xfer_noirq is not needed once we kill the prefetcher */
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.sff_data_xfer = ata_sff_data_xfer32,
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.sff_irq_check = cmd640_sff_irq_check,
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.qc_issue = cmd640_qc_issue,
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.cable_detect = ata_cable_40wire,
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.set_piomode = cmd640_set_piomode,
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.port_start = cmd640_port_start,
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};
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static void cmd640_hardware_init(struct pci_dev *pdev)
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{
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u8 ctrl;
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/* CMD640 detected, commiserations */
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pci_write_config_byte(pdev, 0x5B, 0x00);
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/* PIO0 command cycles */
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pci_write_config_byte(pdev, CMDTIM, 0);
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/* 512 byte bursts (sector) */
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pci_write_config_byte(pdev, BRST, 0x40);
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/*
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* A reporter a long time ago
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* Had problems with the data fifo
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* So don't run the risk
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* Of putting crap on the disk
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* For its better just to go slow
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*/
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/* Do channel 0 */
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pci_read_config_byte(pdev, CNTRL, &ctrl);
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pci_write_config_byte(pdev, CNTRL, ctrl | 0xC0);
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/* Ditto for channel 1 */
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pci_read_config_byte(pdev, ARTIM23, &ctrl);
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ctrl |= 0x0C;
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pci_write_config_byte(pdev, ARTIM23, ctrl);
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}
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static int cmd640_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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static const struct ata_port_info info = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.port_ops = &cmd640_port_ops
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};
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const struct ata_port_info *ppi[] = { &info, NULL };
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int rc;
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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cmd640_hardware_init(pdev);
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return ata_pci_sff_init_one(pdev, ppi, &cmd640_sht, NULL, 0);
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}
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#ifdef CONFIG_PM_SLEEP
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static int cmd640_reinit_one(struct pci_dev *pdev)
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{
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struct ata_host *host = pci_get_drvdata(pdev);
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int rc;
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rc = ata_pci_device_do_resume(pdev);
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if (rc)
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return rc;
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cmd640_hardware_init(pdev);
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ata_host_resume(host);
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return 0;
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}
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#endif
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static const struct pci_device_id cmd640[] = {
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{ PCI_VDEVICE(CMD, 0x640), 0 },
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{ },
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};
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static struct pci_driver cmd640_pci_driver = {
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.name = DRV_NAME,
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.id_table = cmd640,
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.probe = cmd640_init_one,
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.remove = ata_pci_remove_one,
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#ifdef CONFIG_PM_SLEEP
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.suspend = ata_pci_device_suspend,
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.resume = cmd640_reinit_one,
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#endif
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};
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module_pci_driver(cmd640_pci_driver);
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for CMD640 PATA controllers");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, cmd640);
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MODULE_VERSION(DRV_VERSION);
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