131 lines
4 KiB
C
131 lines
4 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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#ifndef __AMDGPU_GMC_H__
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#define __AMDGPU_GMC_H__
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#include <linux/types.h>
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#include "amdgpu_irq.h"
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struct firmware;
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/*
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* VMHUB structures, functions & helpers
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*/
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struct amdgpu_vmhub {
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uint32_t ctx0_ptb_addr_lo32;
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uint32_t ctx0_ptb_addr_hi32;
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uint32_t vm_inv_eng0_req;
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uint32_t vm_inv_eng0_ack;
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uint32_t vm_context0_cntl;
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uint32_t vm_l2_pro_fault_status;
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uint32_t vm_l2_pro_fault_cntl;
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};
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/*
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* GPU MC structures, functions & helpers
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*/
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struct amdgpu_gmc_funcs {
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/* flush the vm tlb via mmio */
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void (*flush_gpu_tlb)(struct amdgpu_device *adev,
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uint32_t vmid);
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/* flush the vm tlb via ring */
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uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
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uint64_t pd_addr);
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/* Change the VMID -> PASID mapping */
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void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
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unsigned pasid);
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/* write pte/pde updates using the cpu */
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int (*set_pte_pde)(struct amdgpu_device *adev,
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void *cpu_pt_addr, /* cpu addr of page table */
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uint32_t gpu_page_idx, /* pte/pde to update */
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uint64_t addr, /* addr to write into pte/pde */
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uint64_t flags); /* access flags */
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/* enable/disable PRT support */
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void (*set_prt)(struct amdgpu_device *adev, bool enable);
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/* set pte flags based per asic */
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uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
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uint32_t flags);
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/* get the pde for a given mc addr */
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void (*get_vm_pde)(struct amdgpu_device *adev, int level,
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u64 *dst, u64 *flags);
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};
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struct amdgpu_gmc {
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resource_size_t aper_size;
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resource_size_t aper_base;
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/* for some chips with <= 32MB we need to lie
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* about vram size near mc fb location */
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u64 mc_vram_size;
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u64 visible_vram_size;
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u64 gart_size;
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u64 gart_start;
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u64 gart_end;
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u64 vram_start;
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u64 vram_end;
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unsigned vram_width;
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u64 real_vram_size;
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int vram_mtrr;
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u64 mc_mask;
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const struct firmware *fw; /* MC firmware */
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uint32_t fw_version;
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struct amdgpu_irq_src vm_fault;
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uint32_t vram_type;
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uint32_t srbm_soft_reset;
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bool prt_warning;
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uint64_t stolen_size;
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uint32_t sdpif_register;
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/* apertures */
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u64 shared_aperture_start;
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u64 shared_aperture_end;
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u64 private_aperture_start;
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u64 private_aperture_end;
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/* protects concurrent invalidation */
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spinlock_t invalidate_lock;
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bool translate_further;
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struct kfd_vm_fault_info *vm_fault_info;
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atomic_t vm_fault_info_updated;
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const struct amdgpu_gmc_funcs *gmc_funcs;
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};
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/**
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* amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
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*
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* @adev: amdgpu_device pointer
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*
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* Returns:
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* True if full VRAM is visible through the BAR
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*/
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static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
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{
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WARN_ON(gmc->real_vram_size < gmc->visible_vram_size);
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return (gmc->real_vram_size == gmc->visible_vram_size);
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}
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#endif
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