338 lines
10 KiB
C
338 lines
10 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König
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*/
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#ifndef __AMDGPU_VM_H__
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#define __AMDGPU_VM_H__
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#include <linux/idr.h>
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#include <linux/kfifo.h>
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#include <linux/rbtree.h>
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#include <drm/gpu_scheduler.h>
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#include <drm/drm_file.h>
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#include "amdgpu_sync.h"
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#include "amdgpu_ring.h"
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#include "amdgpu_ids.h"
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struct amdgpu_bo_va;
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struct amdgpu_job;
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struct amdgpu_bo_list_entry;
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/*
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* GPUVM handling
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*/
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/* Maximum number of PTEs the hardware can write with one command */
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#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
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/* number of entries in page table */
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#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
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/* PTBs (Page Table Blocks) need to be aligned to 32K */
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#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
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#define AMDGPU_PTE_VALID (1ULL << 0)
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#define AMDGPU_PTE_SYSTEM (1ULL << 1)
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#define AMDGPU_PTE_SNOOPED (1ULL << 2)
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/* VI only */
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#define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
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#define AMDGPU_PTE_READABLE (1ULL << 5)
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#define AMDGPU_PTE_WRITEABLE (1ULL << 6)
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#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
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/* TILED for VEGA10, reserved for older ASICs */
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#define AMDGPU_PTE_PRT (1ULL << 51)
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/* PDE is handled as PTE for VEGA10 */
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#define AMDGPU_PDE_PTE (1ULL << 54)
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/* PTE is handled as PDE for VEGA10 (Translate Further) */
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#define AMDGPU_PTE_TF (1ULL << 56)
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/* PDE Block Fragment Size for VEGA10 */
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#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
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/* For GFX9 */
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#define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
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#define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)
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#define AMDGPU_MTYPE_NC 0
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#define AMDGPU_MTYPE_CC 2
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#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
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| AMDGPU_PTE_SNOOPED \
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| AMDGPU_PTE_EXECUTABLE \
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| AMDGPU_PTE_READABLE \
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| AMDGPU_PTE_WRITEABLE \
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| AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC))
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/* How to programm VM fault handling */
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#define AMDGPU_VM_FAULT_STOP_NEVER 0
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#define AMDGPU_VM_FAULT_STOP_FIRST 1
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#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
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/* max number of VMHUB */
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#define AMDGPU_MAX_VMHUBS 2
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#define AMDGPU_GFXHUB 0
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#define AMDGPU_MMHUB 1
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/* hardcode that limit for now */
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#define AMDGPU_VA_RESERVED_SIZE (1ULL << 20)
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/* VA hole for 48bit addresses on Vega10 */
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#define AMDGPU_VA_HOLE_START 0x0000800000000000ULL
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#define AMDGPU_VA_HOLE_END 0xffff800000000000ULL
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/*
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* Hardware is programmed as if the hole doesn't exists with start and end
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* address values.
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*
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* This mask is used to remove the upper 16bits of the VA and so come up with
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* the linear addr value.
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*/
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#define AMDGPU_VA_HOLE_MASK 0x0000ffffffffffffULL
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/* max vmids dedicated for process */
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#define AMDGPU_VM_MAX_RESERVED_VMID 1
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#define AMDGPU_VM_CONTEXT_GFX 0
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#define AMDGPU_VM_CONTEXT_COMPUTE 1
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/* See vm_update_mode */
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#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
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#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
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/* VMPT level enumerate, and the hiberachy is:
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* PDB2->PDB1->PDB0->PTB
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*/
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enum amdgpu_vm_level {
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AMDGPU_VM_PDB2,
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AMDGPU_VM_PDB1,
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AMDGPU_VM_PDB0,
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AMDGPU_VM_PTB
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};
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/* base structure for tracking BO usage in a VM */
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struct amdgpu_vm_bo_base {
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/* constant after initialization */
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struct amdgpu_vm *vm;
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struct amdgpu_bo *bo;
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/* protected by bo being reserved */
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struct list_head bo_list;
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/* protected by spinlock */
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struct list_head vm_status;
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/* protected by the BO being reserved */
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bool moved;
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};
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struct amdgpu_vm_pt {
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struct amdgpu_vm_bo_base base;
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bool huge;
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/* array of page tables, one for each directory entry */
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struct amdgpu_vm_pt *entries;
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};
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#define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))
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#define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
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#define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL)
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struct amdgpu_task_info {
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char process_name[TASK_COMM_LEN];
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char task_name[TASK_COMM_LEN];
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pid_t pid;
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pid_t tgid;
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};
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struct amdgpu_vm {
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/* tree of virtual addresses mapped */
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struct rb_root_cached va;
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/* BOs who needs a validation */
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struct list_head evicted;
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/* PT BOs which relocated and their parent need an update */
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struct list_head relocated;
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/* BOs moved, but not yet updated in the PT */
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struct list_head moved;
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spinlock_t moved_lock;
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/* All BOs of this VM not currently in the state machine */
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struct list_head idle;
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/* BO mappings freed, but not yet updated in the PT */
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struct list_head freed;
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/* contains the page directory */
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struct amdgpu_vm_pt root;
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struct dma_fence *last_update;
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/* Scheduler entity for page table updates */
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struct drm_sched_entity entity;
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unsigned int pasid;
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/* dedicated to vm */
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struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS];
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/* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
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bool use_cpu_for_update;
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/* Flag to indicate ATS support from PTE for GFX9 */
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bool pte_support_ats;
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/* Up to 128 pending retry page faults */
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DECLARE_KFIFO(faults, u64, 128);
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/* Limit non-retry fault storms */
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unsigned int fault_credit;
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/* Points to the KFD process VM info */
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struct amdkfd_process_info *process_info;
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/* List node in amdkfd_process_info.vm_list_head */
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struct list_head vm_list_node;
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/* Valid while the PD is reserved or fenced */
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uint64_t pd_phys_addr;
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/* Some basic info about the task */
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struct amdgpu_task_info task_info;
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};
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struct amdgpu_vm_manager {
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/* Handling of VMIDs */
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struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
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/* Handling of VM fences */
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u64 fence_context;
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unsigned seqno[AMDGPU_MAX_RINGS];
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uint64_t max_pfn;
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uint32_t num_level;
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uint32_t block_size;
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uint32_t fragment_size;
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enum amdgpu_vm_level root_level;
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/* vram base address for page table entry */
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u64 vram_base_offset;
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/* vm pte handling */
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const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
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struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
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unsigned vm_pte_num_rings;
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atomic_t vm_pte_next_ring;
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/* partial resident texture handling */
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spinlock_t prt_lock;
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atomic_t num_prt_users;
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/* controls how VM page tables are updated for Graphics and Compute.
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* BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
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* BIT1[= 0] Compute updated by SDMA [= 1] by CPU
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*/
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int vm_update_mode;
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/* PASID to VM mapping, will be used in interrupt context to
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* look up VM of a page fault
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*/
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struct idr pasid_idr;
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spinlock_t pasid_lock;
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};
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void amdgpu_vm_manager_init(struct amdgpu_device *adev);
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void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
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int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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int vm_context, unsigned int pasid);
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int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
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void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
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bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
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unsigned int pasid);
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void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
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struct list_head *validated,
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struct amdgpu_bo_list_entry *entry);
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bool amdgpu_vm_ready(struct amdgpu_vm *vm);
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int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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int (*callback)(void *p, struct amdgpu_bo *bo),
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void *param);
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int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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uint64_t saddr, uint64_t size);
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int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
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int amdgpu_vm_update_directories(struct amdgpu_device *adev,
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struct amdgpu_vm *vm);
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int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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struct dma_fence **fence);
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int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
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struct amdgpu_vm *vm);
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int amdgpu_vm_bo_update(struct amdgpu_device *adev,
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struct amdgpu_bo_va *bo_va,
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bool clear);
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void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
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struct amdgpu_bo *bo, bool evicted);
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struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
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struct amdgpu_bo *bo);
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struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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struct amdgpu_bo *bo);
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int amdgpu_vm_bo_map(struct amdgpu_device *adev,
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struct amdgpu_bo_va *bo_va,
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uint64_t addr, uint64_t offset,
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uint64_t size, uint64_t flags);
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int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
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struct amdgpu_bo_va *bo_va,
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uint64_t addr, uint64_t offset,
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uint64_t size, uint64_t flags);
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int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
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struct amdgpu_bo_va *bo_va,
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uint64_t addr);
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int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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uint64_t saddr, uint64_t size);
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struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
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uint64_t addr);
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void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
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void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
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struct amdgpu_bo_va *bo_va);
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void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
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uint32_t fragment_size_default, unsigned max_level,
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unsigned max_bits);
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int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
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bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
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struct amdgpu_job *job);
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void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
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void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
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struct amdgpu_task_info *task_info);
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void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
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#endif
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