246 lines
7.1 KiB
C
246 lines
7.1 KiB
C
/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2014 Endless Mobile
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Written by:
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* Jasper St. Pierre <jstpierre@mecheye.net>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_rect.h>
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#include "meson_plane.h"
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#include "meson_vpp.h"
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#include "meson_viu.h"
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#include "meson_canvas.h"
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#include "meson_registers.h"
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struct meson_plane {
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struct drm_plane base;
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struct meson_drm *priv;
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};
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#define to_meson_plane(x) container_of(x, struct meson_plane, base)
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static int meson_plane_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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struct drm_crtc_state *crtc_state;
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if (!state->crtc)
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return 0;
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crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
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if (IS_ERR(crtc_state))
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return PTR_ERR(crtc_state);
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return drm_atomic_helper_check_plane_state(state, crtc_state,
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DRM_PLANE_HELPER_NO_SCALING,
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DRM_PLANE_HELPER_NO_SCALING,
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true, true);
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}
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/* Takes a fixed 16.16 number and converts it to integer. */
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static inline int64_t fixed16_to_int(int64_t value)
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{
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return value >> 16;
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}
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static void meson_plane_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct meson_plane *meson_plane = to_meson_plane(plane);
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = state->fb;
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struct meson_drm *priv = meson_plane->priv;
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struct drm_gem_cma_object *gem;
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struct drm_rect src = {
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.x1 = (state->src_x),
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.y1 = (state->src_y),
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.x2 = (state->src_x + state->src_w),
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.y2 = (state->src_y + state->src_h),
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};
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struct drm_rect dest = {
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.x1 = state->crtc_x,
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.y1 = state->crtc_y,
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.x2 = state->crtc_x + state->crtc_w,
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.y2 = state->crtc_y + state->crtc_h,
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};
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unsigned long flags;
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/*
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* Update Coordinates
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* Update Formats
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* Update Buffer
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* Enable Plane
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*/
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spin_lock_irqsave(&priv->drm->event_lock, flags);
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/* Enable OSD and BLK0, set max global alpha */
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priv->viu.osd1_ctrl_stat = OSD_ENABLE |
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(0xFF << OSD_GLOBAL_ALPHA_SHIFT) |
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OSD_BLK0_ENABLE;
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/* Set up BLK0 to point to the right canvas */
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priv->viu.osd1_blk0_cfg[0] = ((MESON_CANVAS_ID_OSD1 << OSD_CANVAS_SEL) |
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OSD_ENDIANNESS_LE);
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/* On GXBB, Use the old non-HDR RGB2YUV converter */
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if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
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priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
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switch (fb->format->format) {
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case DRM_FORMAT_XRGB8888:
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/* For XRGB, replace the pixel's alpha by 0xFF */
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writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
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OSD_COLOR_MATRIX_32_ARGB;
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break;
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case DRM_FORMAT_XBGR8888:
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/* For XRGB, replace the pixel's alpha by 0xFF */
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writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
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OSD_COLOR_MATRIX_32_ABGR;
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break;
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case DRM_FORMAT_ARGB8888:
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/* For ARGB, use the pixel's alpha */
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writel_bits_relaxed(OSD_REPLACE_EN, 0,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
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OSD_COLOR_MATRIX_32_ARGB;
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break;
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case DRM_FORMAT_ABGR8888:
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/* For ARGB, use the pixel's alpha */
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writel_bits_relaxed(OSD_REPLACE_EN, 0,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
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OSD_COLOR_MATRIX_32_ABGR;
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break;
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case DRM_FORMAT_RGB888:
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 |
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OSD_COLOR_MATRIX_24_RGB;
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break;
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case DRM_FORMAT_RGB565:
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 |
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OSD_COLOR_MATRIX_16_RGB565;
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break;
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};
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if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
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priv->viu.osd1_interlace = true;
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dest.y1 /= 2;
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dest.y2 /= 2;
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} else
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priv->viu.osd1_interlace = false;
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/*
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* The format of these registers is (x2 << 16 | x1),
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* where x2 is exclusive.
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* e.g. +30x1920 would be (1919 << 16) | 30
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*/
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priv->viu.osd1_blk0_cfg[1] = ((fixed16_to_int(src.x2) - 1) << 16) |
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fixed16_to_int(src.x1);
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priv->viu.osd1_blk0_cfg[2] = ((fixed16_to_int(src.y2) - 1) << 16) |
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fixed16_to_int(src.y1);
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priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
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priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
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/* Update Canvas with buffer address */
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gem = drm_fb_cma_get_gem_obj(fb, 0);
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priv->viu.osd1_addr = gem->paddr;
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priv->viu.osd1_stride = fb->pitches[0];
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priv->viu.osd1_height = fb->height;
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spin_unlock_irqrestore(&priv->drm->event_lock, flags);
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}
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static void meson_plane_atomic_disable(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct meson_plane *meson_plane = to_meson_plane(plane);
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struct meson_drm *priv = meson_plane->priv;
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/* Disable OSD1 */
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writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
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priv->io_base + _REG(VPP_MISC));
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}
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static const struct drm_plane_helper_funcs meson_plane_helper_funcs = {
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.atomic_check = meson_plane_atomic_check,
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.atomic_disable = meson_plane_atomic_disable,
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.atomic_update = meson_plane_atomic_update,
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};
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static const struct drm_plane_funcs meson_plane_funcs = {
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.update_plane = drm_atomic_helper_update_plane,
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.disable_plane = drm_atomic_helper_disable_plane,
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.destroy = drm_plane_cleanup,
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.reset = drm_atomic_helper_plane_reset,
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.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
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};
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static const uint32_t supported_drm_formats[] = {
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_RGB565,
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};
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int meson_plane_create(struct meson_drm *priv)
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{
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struct meson_plane *meson_plane;
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struct drm_plane *plane;
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meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane),
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GFP_KERNEL);
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if (!meson_plane)
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return -ENOMEM;
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meson_plane->priv = priv;
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plane = &meson_plane->base;
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drm_universal_plane_init(priv->drm, plane, 0xFF,
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&meson_plane_funcs,
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supported_drm_formats,
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ARRAY_SIZE(supported_drm_formats),
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NULL,
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DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane");
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drm_plane_helper_add(plane, &meson_plane_helper_funcs);
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priv->primary_plane = plane;
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return 0;
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}
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