167 lines
5.8 KiB
C
167 lines
5.8 KiB
C
/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2014 Endless Mobile
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <drm/drmP.h>
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#include "meson_drv.h"
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#include "meson_vpp.h"
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#include "meson_registers.h"
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/**
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* DOC: Video Post Processing
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*
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* VPP Handles all the Post Processing after the Scanout from the VIU
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* We handle the following post processings :
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*
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* - Postblend, Blends the OSD1 only
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* We exclude OSD2, VS1, VS1 and Preblend output
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* - Vertical OSD Scaler for OSD1 only, we disable vertical scaler and
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* use it only for interlace scanout
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* - Intermediate FIFO with default Amlogic values
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*
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* What is missing :
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*
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* - Preblend for video overlay pre-scaling
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* - OSD2 support for cursor framebuffer
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* - Video pre-scaling before postblend
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* - Full Vertical/Horizontal OSD scaling to support TV overscan
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* - HDR conversion
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*/
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void meson_vpp_setup_mux(struct meson_drm *priv, unsigned int mux)
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{
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writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL));
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}
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/*
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* When the output is interlaced, the OSD must switch between
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* each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0
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* at each vsync.
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* But the vertical scaler can provide such funtionnality if
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* is configured for 2:1 scaling with interlace options enabled.
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*/
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void meson_vpp_setup_interlace_vscaler_osd1(struct meson_drm *priv,
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struct drm_rect *input)
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{
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writel_relaxed(BIT(3) /* Enable scaler */ |
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BIT(2), /* Select OSD1 */
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priv->io_base + _REG(VPP_OSD_SC_CTRL0));
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writel_relaxed(((drm_rect_width(input) - 1) << 16) |
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(drm_rect_height(input) - 1),
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priv->io_base + _REG(VPP_OSD_SCI_WH_M1));
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/* 2:1 scaling */
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writel_relaxed(((input->x1) << 16) | (input->x2),
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priv->io_base + _REG(VPP_OSD_SCO_H_START_END));
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writel_relaxed(((input->y1 >> 1) << 16) | (input->y2 >> 1),
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priv->io_base + _REG(VPP_OSD_SCO_V_START_END));
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/* 2:1 scaling values */
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writel_relaxed(BIT(16), priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));
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writel_relaxed(BIT(25), priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));
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writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
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writel_relaxed((4 << 0) /* osd_vsc_bank_length */ |
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(4 << 3) /* osd_vsc_top_ini_rcv_num0 */ |
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(1 << 8) /* osd_vsc_top_rpt_p0_num0 */ |
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(6 << 11) /* osd_vsc_bot_ini_rcv_num0 */ |
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(2 << 16) /* osd_vsc_bot_rpt_p0_num0 */ |
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BIT(23) /* osd_prog_interlace */ |
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BIT(24), /* Enable vertical scaler */
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priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
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}
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void meson_vpp_disable_interlace_vscaler_osd1(struct meson_drm *priv)
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{
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writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
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writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
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writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
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}
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static unsigned int vpp_filter_coefs_4point_bspline[] = {
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0x15561500, 0x14561600, 0x13561700, 0x12561800,
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0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00,
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0x0f531e00, 0x0e531f00, 0x0d522100, 0x0c522200,
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0x0b522300, 0x0b512400, 0x0a502600, 0x0a4f2700,
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0x094e2900, 0x084e2a00, 0x084d2b00, 0x074c2c01,
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0x074b2d01, 0x064a2f01, 0x06493001, 0x05483201,
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0x05473301, 0x05463401, 0x04453601, 0x04433702,
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0x04423802, 0x03413a02, 0x03403b02, 0x033f3c02,
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0x033d3d03
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};
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static void meson_vpp_write_scaling_filter_coefs(struct meson_drm *priv,
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const unsigned int *coefs,
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bool is_horizontal)
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{
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int i;
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writel_relaxed(is_horizontal ? BIT(8) : 0,
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priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX));
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for (i = 0; i < 33; i++)
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writel_relaxed(coefs[i],
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priv->io_base + _REG(VPP_OSD_SCALE_COEF));
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}
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void meson_vpp_init(struct meson_drm *priv)
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{
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/* set dummy data default YUV black */
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if (meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
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writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
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else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu")) {
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writel_bits_relaxed(0xff << 16, 0xff << 16,
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priv->io_base + _REG(VIU_MISC_CTRL1));
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writel_relaxed(0x20000, priv->io_base + _REG(VPP_DOLBY_CTRL));
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writel_relaxed(0x1020080,
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priv->io_base + _REG(VPP_DUMMY_DATA1));
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}
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/* Initialize vpu fifo control registers */
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writel_relaxed(readl_relaxed(priv->io_base + _REG(VPP_OFIFO_SIZE)) |
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0x77f, priv->io_base + _REG(VPP_OFIFO_SIZE));
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writel_relaxed(0x08080808, priv->io_base + _REG(VPP_HOLD_LINES));
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/* Turn off preblend */
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writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0,
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priv->io_base + _REG(VPP_MISC));
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/* Turn off POSTBLEND */
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writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
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priv->io_base + _REG(VPP_MISC));
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/* Force all planes off */
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writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND |
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VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND, 0,
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priv->io_base + _REG(VPP_MISC));
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/* Disable Scalers */
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writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
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writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
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writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
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/* Write in the proper filter coefficients. */
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meson_vpp_write_scaling_filter_coefs(priv,
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vpp_filter_coefs_4point_bspline, false);
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meson_vpp_write_scaling_filter_coefs(priv,
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vpp_filter_coefs_4point_bspline, true);
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}
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