743 lines
21 KiB
C
743 lines
21 KiB
C
/* Driver for Realtek PCI-Express card reader
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*
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* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Author:
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* Wei WANG <wei_wang@realsil.com.cn>
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/rtsx_pci.h>
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#include "rtsx_pcr.h"
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static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
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{
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u8 val;
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rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
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return val & 0x0F;
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}
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static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
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{
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u8 driving_3v3[4][3] = {
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{0x11, 0x11, 0x18},
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{0x55, 0x55, 0x5C},
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{0xFF, 0xFF, 0xFF},
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{0x96, 0x96, 0x96},
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};
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u8 driving_1v8[4][3] = {
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{0xC4, 0xC4, 0xC4},
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{0x3C, 0x3C, 0x3C},
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{0xFE, 0xFE, 0xFE},
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{0xB3, 0xB3, 0xB3},
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};
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u8 (*driving)[3], drive_sel;
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if (voltage == OUTPUT_3V3) {
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driving = driving_3v3;
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drive_sel = pcr->sd30_drive_sel_3v3;
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} else {
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driving = driving_1v8;
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drive_sel = pcr->sd30_drive_sel_1v8;
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}
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
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0xFF, driving[drive_sel][0]);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
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0xFF, driving[drive_sel][1]);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
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0xFF, driving[drive_sel][2]);
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}
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static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
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{
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u32 reg;
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rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
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if (!rtsx_vendor_setting_valid(reg)) {
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pcr_dbg(pcr, "skip fetch vendor setting\n");
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return;
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}
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pcr->aspm_en = rtsx_reg_to_aspm(reg);
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pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
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pcr->card_drive_sel &= 0x3F;
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pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
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rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
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pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
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if (rtsx_reg_check_reverse_socket(reg))
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pcr->flags |= PCR_REVERSE_SOCKET;
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}
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static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
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{
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/* Set relink_time to 0 */
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rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
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rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
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rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
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if (pm_state == HOST_ENTER_S3)
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
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D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
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rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
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}
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static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
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{
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struct rtsx_cr_option *option = &(pcr->option);
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u32 lval;
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if (CHK_PCI_PID(pcr, PID_524A))
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rtsx_pci_read_config_dword(pcr,
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PCR_ASPM_SETTING_REG1, &lval);
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else
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rtsx_pci_read_config_dword(pcr,
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PCR_ASPM_SETTING_REG2, &lval);
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if (lval & ASPM_L1_1_EN_MASK)
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rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
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if (lval & ASPM_L1_2_EN_MASK)
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rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
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if (lval & PM_L1_1_EN_MASK)
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rtsx_set_dev_flag(pcr, PM_L1_1_EN);
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if (lval & PM_L1_2_EN_MASK)
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rtsx_set_dev_flag(pcr, PM_L1_2_EN);
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if (option->ltr_en) {
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u16 val;
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pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
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if (val & PCI_EXP_DEVCTL2_LTR_EN) {
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option->ltr_enabled = true;
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option->ltr_active = true;
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rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
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} else {
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option->ltr_enabled = false;
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}
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}
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}
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static int rts5249_init_from_hw(struct rtsx_pcr *pcr)
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{
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struct rtsx_cr_option *option = &(pcr->option);
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if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
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| PM_L1_1_EN | PM_L1_2_EN))
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option->force_clkreq_0 = false;
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else
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option->force_clkreq_0 = true;
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return 0;
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}
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static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
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{
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struct rtsx_cr_option *option = &(pcr->option);
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rts5249_init_from_cfg(pcr);
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rts5249_init_from_hw(pcr);
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rtsx_pci_init_cmd(pcr);
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/* Rest L1SUB Config */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
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/* Configure GPIO as output */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
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/* Reset ASPM state to default value */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
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/* Switch LDO3318 source from DV33 to card_3v3 */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
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/* LED shine disabled, set initial shine cycle period */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
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/* Configure driving */
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rts5249_fill_driving(pcr, OUTPUT_3V3);
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if (pcr->flags & PCR_REVERSE_SOCKET)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
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/*
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* If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
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* to drive low, and we forcibly request clock.
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*/
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if (option->force_clkreq_0)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
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FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
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FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
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return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
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}
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static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
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{
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int err;
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err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_REV,
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PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
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PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
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PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
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PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
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PHY_REV_STOP_CLKWR);
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if (err < 0)
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return err;
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msleep(1);
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err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
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PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
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PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
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PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
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PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
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PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
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PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
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PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
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PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
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PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
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PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
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PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
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PHY_FLD4_BER_CHK_EN);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
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PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
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PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
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PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
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PHY_FLD3_RXDELINK);
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if (err < 0)
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return err;
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return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
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PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
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PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
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PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
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}
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static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
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}
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static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
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}
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static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
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}
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static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
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}
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static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
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{
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int err;
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x02);
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err = rtsx_pci_send_cmd(pcr, 100);
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if (err < 0)
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return err;
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msleep(5);
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK, SD_VCC_POWER_ON);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x06);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
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{
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK, SD_POWER_OFF);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x00);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
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{
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int err;
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u16 append;
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switch (voltage) {
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case OUTPUT_3V3:
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err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
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PHY_TUNE_VOLTAGE_3V3);
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if (err < 0)
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return err;
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break;
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case OUTPUT_1V8:
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append = PHY_TUNE_D18_1V8;
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if (CHK_PCI_PID(pcr, 0x5249)) {
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err = rtsx_pci_update_phy(pcr, PHY_BACR,
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PHY_BACR_BASIC_MASK, 0);
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if (err < 0)
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return err;
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append = PHY_TUNE_D18_1V7;
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}
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err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK,
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append);
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if (err < 0)
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return err;
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break;
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default:
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pcr_dbg(pcr, "unknown output voltage %d\n", voltage);
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return -EINVAL;
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}
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/* set pad drive */
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rtsx_pci_init_cmd(pcr);
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rts5249_fill_driving(pcr, voltage);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static void rts5249_set_aspm(struct rtsx_pcr *pcr, bool enable)
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{
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struct rtsx_cr_option *option = &pcr->option;
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u8 val = 0;
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if (pcr->aspm_enabled == enable)
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return;
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if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
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if (enable)
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val = pcr->aspm_en;
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rtsx_pci_update_cfg_byte(pcr,
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pcr->pcie_cap + PCI_EXP_LNKCTL,
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ASPM_MASK_NEG, val);
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} else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
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u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
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if (!enable)
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val = FORCE_ASPM_CTL0;
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rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
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}
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pcr->aspm_enabled = enable;
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}
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static const struct pcr_ops rts5249_pcr_ops = {
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.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
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.extra_init_hw = rts5249_extra_init_hw,
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.optimize_phy = rts5249_optimize_phy,
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.turn_on_led = rtsx_base_turn_on_led,
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.turn_off_led = rtsx_base_turn_off_led,
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.enable_auto_blink = rtsx_base_enable_auto_blink,
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.disable_auto_blink = rtsx_base_disable_auto_blink,
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.card_power_on = rtsx_base_card_power_on,
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.card_power_off = rtsx_base_card_power_off,
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.switch_output_voltage = rtsx_base_switch_output_voltage,
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.force_power_down = rtsx_base_force_power_down,
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.set_aspm = rts5249_set_aspm,
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};
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/* SD Pull Control Enable:
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* SD_DAT[3:0] ==> pull up
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* SD_CD ==> pull up
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* SD_WP ==> pull up
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* SD_CMD ==> pull up
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* SD_CLK ==> pull down
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*/
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static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
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0,
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};
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/* SD Pull Control Disable:
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* SD_DAT[3:0] ==> pull down
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* SD_CD ==> pull up
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* SD_WP ==> pull down
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* SD_CMD ==> pull down
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* SD_CLK ==> pull down
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*/
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static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
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|
RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
|
|
0,
|
|
};
|
|
|
|
/* MS Pull Control Enable:
|
|
* MS CD ==> pull up
|
|
* others ==> pull down
|
|
*/
|
|
static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
|
|
RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
|
|
0,
|
|
};
|
|
|
|
/* MS Pull Control Disable:
|
|
* MS CD ==> pull up
|
|
* others ==> pull down
|
|
*/
|
|
static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
|
|
RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
|
|
RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
|
|
0,
|
|
};
|
|
|
|
void rts5249_init_params(struct rtsx_pcr *pcr)
|
|
{
|
|
struct rtsx_cr_option *option = &(pcr->option);
|
|
|
|
pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
|
|
pcr->num_slots = 2;
|
|
pcr->ops = &rts5249_pcr_ops;
|
|
|
|
pcr->flags = 0;
|
|
pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
|
|
pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
|
|
pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
|
|
pcr->aspm_en = ASPM_L1_EN;
|
|
pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
|
|
pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
|
|
|
|
pcr->ic_version = rts5249_get_ic_version(pcr);
|
|
pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
|
|
pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
|
|
pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
|
|
pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
|
|
|
|
pcr->reg_pm_ctrl3 = PM_CTRL3;
|
|
|
|
option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
|
|
| LTR_L1SS_PWR_GATE_EN);
|
|
option->ltr_en = true;
|
|
|
|
/* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */
|
|
option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
|
|
option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
|
|
option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
|
|
option->dev_aspm_mode = DEV_ASPM_DYNAMIC;
|
|
option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
|
|
option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
|
|
option->ltr_l1off_snooze_sspwrgate =
|
|
LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
|
|
}
|
|
|
|
static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
|
|
{
|
|
addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
|
|
|
|
return __rtsx_pci_write_phy_register(pcr, addr, val);
|
|
}
|
|
|
|
static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
|
|
{
|
|
addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
|
|
|
|
return __rtsx_pci_read_phy_register(pcr, addr, val);
|
|
}
|
|
|
|
static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
|
|
{
|
|
int err;
|
|
|
|
err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
|
|
D3_DELINK_MODE_EN, 0x00);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
rtsx_pci_write_phy_register(pcr, PHY_PCR,
|
|
PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
|
|
PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
|
|
rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
|
|
PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
|
|
|
|
if (is_version(pcr, 0x524A, IC_VER_A)) {
|
|
rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
|
|
PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
|
|
rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
|
|
PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
|
|
PHY_SSCCR2_TIME2_WIDTH);
|
|
rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
|
|
PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
|
|
PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
|
|
rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
|
|
PHY_ANA1D_DEBUG_ADDR);
|
|
rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
|
|
PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
|
|
PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
|
|
PHY_DIG1E_RCLK_TX_EN_KEEP |
|
|
PHY_DIG1E_RCLK_TX_TERM_KEEP |
|
|
PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
|
|
PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
|
|
PHY_DIG1E_RX_EN_KEEP);
|
|
}
|
|
|
|
rtsx_pci_write_phy_register(pcr, PHY_ANA08,
|
|
PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
|
|
PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
|
|
{
|
|
rts5249_extra_init_hw(pcr);
|
|
|
|
rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
|
|
FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
|
|
rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
|
|
rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
|
|
LDO_VCC_LMT_EN);
|
|
rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
|
|
if (is_version(pcr, 0x524A, IC_VER_A)) {
|
|
rtsx_pci_write_register(pcr, LDO_DV18_CFG,
|
|
LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
|
|
rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
|
|
LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
|
|
rtsx_pci_write_register(pcr, LDO_VIO_CFG,
|
|
LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
|
|
rtsx_pci_write_register(pcr, LDO_VIO_CFG,
|
|
LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
|
|
rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
|
|
LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
|
|
rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
|
|
SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
|
|
{
|
|
struct rtsx_cr_option *option = &(pcr->option);
|
|
|
|
u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
|
|
int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);
|
|
int aspm_L1_1, aspm_L1_2;
|
|
u8 val = 0;
|
|
|
|
aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
|
|
aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
|
|
|
|
if (active) {
|
|
/* Run, latency: 60us */
|
|
if (aspm_L1_1)
|
|
val = option->ltr_l1off_snooze_sspwrgate;
|
|
} else {
|
|
/* L1off, latency: 300us */
|
|
if (aspm_L1_2)
|
|
val = option->ltr_l1off_sspwrgate;
|
|
}
|
|
|
|
if (aspm_L1_1 || aspm_L1_2) {
|
|
if (rtsx_check_dev_flag(pcr,
|
|
LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) {
|
|
if (card_exist)
|
|
val &= ~L1OFF_MBIAS2_EN_5250;
|
|
else
|
|
val |= L1OFF_MBIAS2_EN_5250;
|
|
}
|
|
}
|
|
rtsx_set_l1off_sub(pcr, val);
|
|
}
|
|
|
|
static const struct pcr_ops rts524a_pcr_ops = {
|
|
.write_phy = rts524a_write_phy,
|
|
.read_phy = rts524a_read_phy,
|
|
.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
|
|
.extra_init_hw = rts524a_extra_init_hw,
|
|
.optimize_phy = rts524a_optimize_phy,
|
|
.turn_on_led = rtsx_base_turn_on_led,
|
|
.turn_off_led = rtsx_base_turn_off_led,
|
|
.enable_auto_blink = rtsx_base_enable_auto_blink,
|
|
.disable_auto_blink = rtsx_base_disable_auto_blink,
|
|
.card_power_on = rtsx_base_card_power_on,
|
|
.card_power_off = rtsx_base_card_power_off,
|
|
.switch_output_voltage = rtsx_base_switch_output_voltage,
|
|
.force_power_down = rtsx_base_force_power_down,
|
|
.set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
|
|
.set_aspm = rts5249_set_aspm,
|
|
};
|
|
|
|
void rts524a_init_params(struct rtsx_pcr *pcr)
|
|
{
|
|
rts5249_init_params(pcr);
|
|
pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
|
|
pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
|
|
pcr->option.ltr_l1off_snooze_sspwrgate =
|
|
LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
|
|
|
|
pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
|
|
pcr->ops = &rts524a_pcr_ops;
|
|
}
|
|
|
|
static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
|
|
{
|
|
rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
|
|
LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
|
|
return rtsx_base_card_power_on(pcr, card);
|
|
}
|
|
|
|
static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
|
|
{
|
|
switch (voltage) {
|
|
case OUTPUT_3V3:
|
|
rtsx_pci_write_register(pcr, LDO_CONFIG2,
|
|
LDO_D3318_MASK, LDO_D3318_33V);
|
|
rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
|
|
break;
|
|
case OUTPUT_1V8:
|
|
rtsx_pci_write_register(pcr, LDO_CONFIG2,
|
|
LDO_D3318_MASK, LDO_D3318_18V);
|
|
rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
|
|
SD_IO_USING_1V8);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
rtsx_pci_init_cmd(pcr);
|
|
rts5249_fill_driving(pcr, voltage);
|
|
return rtsx_pci_send_cmd(pcr, 100);
|
|
}
|
|
|
|
static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
|
|
{
|
|
int err;
|
|
|
|
err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
|
|
D3_DELINK_MODE_EN, 0x00);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
|
|
_PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
|
|
_PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
|
|
_PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
|
|
|
|
rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
|
|
_PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
|
|
_PHY_CMU_DEBUG_EN);
|
|
|
|
if (is_version(pcr, 0x525A, IC_VER_A))
|
|
rtsx_pci_write_phy_register(pcr, _PHY_REV0,
|
|
_PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
|
|
_PHY_REV0_CDR_RX_IDLE_BYPASS);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
|
|
{
|
|
rts5249_extra_init_hw(pcr);
|
|
|
|
rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
|
|
if (is_version(pcr, 0x525A, IC_VER_A)) {
|
|
rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
|
|
L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
|
|
rtsx_pci_write_register(pcr, RREF_CFG,
|
|
RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
|
|
rtsx_pci_write_register(pcr, LDO_VIO_CFG,
|
|
LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
|
|
rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
|
|
LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
|
|
rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
|
|
LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
|
|
rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
|
|
LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
|
|
rtsx_pci_write_register(pcr, OOBS_CONFIG,
|
|
OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pcr_ops rts525a_pcr_ops = {
|
|
.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
|
|
.extra_init_hw = rts525a_extra_init_hw,
|
|
.optimize_phy = rts525a_optimize_phy,
|
|
.turn_on_led = rtsx_base_turn_on_led,
|
|
.turn_off_led = rtsx_base_turn_off_led,
|
|
.enable_auto_blink = rtsx_base_enable_auto_blink,
|
|
.disable_auto_blink = rtsx_base_disable_auto_blink,
|
|
.card_power_on = rts525a_card_power_on,
|
|
.card_power_off = rtsx_base_card_power_off,
|
|
.switch_output_voltage = rts525a_switch_output_voltage,
|
|
.force_power_down = rtsx_base_force_power_down,
|
|
.set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0,
|
|
.set_aspm = rts5249_set_aspm,
|
|
};
|
|
|
|
void rts525a_init_params(struct rtsx_pcr *pcr)
|
|
{
|
|
rts5249_init_params(pcr);
|
|
pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11);
|
|
pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF;
|
|
pcr->option.ltr_l1off_snooze_sspwrgate =
|
|
LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF;
|
|
|
|
pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
|
|
pcr->ops = &rts525a_pcr_ops;
|
|
}
|