966 lines
21 KiB
C
966 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/cpu.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip/mtk-gic-extend.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdesc.h>
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#ifdef CONFIG_MTK_IN_HOUSE_TEE_SUPPORT
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#include <trustzone/kree/tz_irq.h>
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#endif
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#if defined(CONFIG_FIQ_GLUE)
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#include <asm/fiq.h>
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#include <asm/fiq_glue.h>
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#endif
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void __iomem *GIC_DIST_BASE;
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void __iomem *GIC_CPU_BASE;
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void __iomem *INT_POL_CTL0;
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/**
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* get_hardware_irq - get a hardware interrupt num
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* @virq: a linux irq
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*
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*/
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unsigned int get_hardware_irq(unsigned int virq)
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{
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struct irq_desc *desc = irq_to_desc(virq);
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struct irq_data *data, *tdata = NULL;
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if (desc)
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tdata = data = &desc->irq_data;
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else
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return -EINVAL;
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#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
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for (data = data->parent_data; data; data = data->parent_data)
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tdata = data;
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#endif
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if (tdata)
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return tdata->hwirq;
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else
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return -EINVAL;
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}
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/*
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* mt_irq_mask_all: disable all interrupts
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* @mask: pointer to struct mtk_irq_mask for storing the original mask value.
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* Return 0 for success; return negative values for failure.
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* (This is ONLY used for the idle current measurement by the factory mode.)
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*/
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int mt_irq_mask_all(struct mtk_irq_mask *mask)
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{
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void __iomem *dist_base;
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dist_base = GIC_DIST_BASE;
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if (mask) {
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/*
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* #if defined(CONFIG_FIQ_GLUE)
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* local_fiq_disable();
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* #endif
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*/
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mask->mask0 = readl((dist_base + GIC_DIST_ENABLE_SET));
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mask->mask1 = readl((dist_base + GIC_DIST_ENABLE_SET + 0x4));
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mask->mask2 = readl((dist_base + GIC_DIST_ENABLE_SET + 0x8));
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mask->mask3 = readl((dist_base + GIC_DIST_ENABLE_SET + 0xC));
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mask->mask4 = readl((dist_base + GIC_DIST_ENABLE_SET + 0x10));
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mask->mask5 = readl((dist_base + GIC_DIST_ENABLE_SET + 0x14));
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mask->mask6 = readl((dist_base + GIC_DIST_ENABLE_SET + 0x18));
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mask->mask7 = readl((dist_base + GIC_DIST_ENABLE_SET + 0x1C));
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mask->mask8 = readl((dist_base + GIC_DIST_ENABLE_SET + 0x20));
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writel(0xFFFFFFFF, (dist_base + GIC_DIST_ENABLE_CLEAR));
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writel(0xFFFFFFFF, (dist_base + GIC_DIST_ENABLE_CLEAR + 0x4));
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writel(0xFFFFFFFF, (dist_base + GIC_DIST_ENABLE_CLEAR + 0x8));
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writel(0xFFFFFFFF, (dist_base + GIC_DIST_ENABLE_CLEAR + 0xC));
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writel(0xFFFFFFFF, (dist_base + GIC_DIST_ENABLE_CLEAR + 0x10));
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writel(0xFFFFFFFF, (dist_base + GIC_DIST_ENABLE_CLEAR + 0x14));
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writel(0xFFFFFFFF, (dist_base + GIC_DIST_ENABLE_CLEAR + 0x18));
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writel(0xFFFFFFFF, (dist_base + GIC_DIST_ENABLE_CLEAR + 0x1C));
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writel(0xFFFFFFFF, (dist_base + GIC_DIST_ENABLE_CLEAR + 0x20));
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/* add memory barrier */
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mb();
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/*
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* #if defined(CONFIG_FIQ_GLUE)
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* local_fiq_enable();
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* #endif
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*/
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mask->header = IRQ_MASK_HEADER;
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mask->footer = IRQ_MASK_FOOTER;
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return 0;
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} else {
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return -1;
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}
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}
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/*
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* mt_irq_mask_restore: restore all interrupts
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* @mask: pointer to struct mtk_irq_mask for storing the original mask value.
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* Return 0 for success; return negative values for failure.
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* (This is ONLY used for the idle current measurement by the factory mode.)
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*/
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int mt_irq_mask_restore(struct mtk_irq_mask *mask)
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{
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void __iomem *dist_base;
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dist_base = GIC_DIST_BASE;
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if (!mask)
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return -1;
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if (mask->header != IRQ_MASK_HEADER)
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return -1;
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if (mask->footer != IRQ_MASK_FOOTER)
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return -1;
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/*
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* #if defined(CONFIG_FIQ_GLUE)
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* local_fiq_disable();
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* #endif
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*/
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writel(mask->mask0, (dist_base + GIC_DIST_ENABLE_SET));
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writel(mask->mask1, (dist_base + GIC_DIST_ENABLE_SET + 0x4));
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writel(mask->mask2, (dist_base + GIC_DIST_ENABLE_SET + 0x8));
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writel(mask->mask3, (dist_base + GIC_DIST_ENABLE_SET + 0xC));
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writel(mask->mask4, (dist_base + GIC_DIST_ENABLE_SET + 0x10));
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writel(mask->mask5, (dist_base + GIC_DIST_ENABLE_SET + 0x14));
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writel(mask->mask6, (dist_base + GIC_DIST_ENABLE_SET + 0x18));
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writel(mask->mask7, (dist_base + GIC_DIST_ENABLE_SET + 0x1C));
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writel(mask->mask8, (dist_base + GIC_DIST_ENABLE_SET + 0x20));
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/* add memory barrier */
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mb();
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/*
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* #if defined(CONFIG_FIQ_GLUE)
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* local_fiq_enable();
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* #endif
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*/
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return 0;
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}
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/*
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* mt_irq_set_pending_for_sleep: pending an interrupt for the sleep
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* manager's use
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* @irq: interrupt id
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* (THIS IS ONLY FOR SLEEP FUNCTION USE. DO NOT USE IT YOURSELF!)
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*/
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void mt_irq_set_pending_for_sleep(unsigned int irq)
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{
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void __iomem *dist_base;
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u32 mask = 1 << (irq % 32);
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dist_base = GIC_DIST_BASE;
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if (irq < 16) {
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pr_info("Fail to set a pending on interrupt %d\n", irq);
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return;
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}
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writel(mask, dist_base + GIC_DIST_PENDING_SET + irq / 32 * 4);
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pr_debug("irq:%d, 0x%p=0x%x\n", irq,
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dist_base + GIC_DIST_PENDING_SET + irq / 32 * 4, mask);
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/* add memory barrier */
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mb();
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}
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u32 mt_irq_get_pending_hw(unsigned int irq)
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{
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void __iomem *dist_base;
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u32 bit = 1 << (irq % 32);
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dist_base = GIC_DIST_BASE;
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return (readl_relaxed(dist_base + GIC_DIST_PENDING_SET + irq / 32 * 4)
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& bit) ? 1 : 0;
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}
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void mt_irq_set_pending_hw(unsigned int irq)
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{
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void __iomem *dist_base;
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u32 bit = 1 << (irq % 32);
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dist_base = GIC_DIST_BASE;
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writel(bit, dist_base + GIC_DIST_PENDING_SET + irq / 32 * 4);
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}
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u32 mt_irq_get_pol_hw(u32 hwirq)
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{
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u32 reg;
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void __iomem *base = INT_POL_CTL0;
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if (hwirq < 32) {
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pr_info("Fail to set polarity of interrupt %d\n", hwirq);
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return 0;
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}
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reg = ((hwirq - 32)/32);
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return readl_relaxed(base + reg*4);
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}
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u32 mt_irq_get_pending_vec(u32 start_irq)
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{
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void __iomem *base = 0;
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u32 pending_vec = 0;
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u32 reg = start_irq/32;
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u32 LSB_num, MSB_num;
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u32 LSB_vec, MSB_vec;
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if (start_irq >= 32)
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base = GIC_DIST_BASE;
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else
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return -EINVAL;
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/* if start_irq is not aligned 32, do some assembling */
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MSB_num = start_irq%32;
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if (MSB_num != 0) {
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LSB_num = 32 - MSB_num;
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LSB_vec = readl_relaxed(base + GIC_DIST_PENDING_SET + reg*4)
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>>MSB_num;
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MSB_vec = readl_relaxed(base + GIC_DIST_PENDING_SET + (reg+1)*4)
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<<LSB_num;
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pending_vec = MSB_vec | LSB_vec;
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} else {
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pending_vec = readl_relaxed(base + GIC_DIST_PENDING_SET +
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reg*4);
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}
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return pending_vec;
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}
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/*
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* mt_irq_unmask_for_sleep: enable an interrupt for the sleep manager's use
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* @irq: interrupt id
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* (THIS IS ONLY FOR SLEEP FUNCTION USE. DO NOT USE IT YOURSELF!)
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*/
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void mt_irq_unmask_for_sleep(unsigned int virq)
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{
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u32 mask;
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void __iomem *dist_base;
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unsigned int irq = get_hardware_irq(virq);
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if (irq < 0)
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return;
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mask = 1 << (irq % 32);
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dist_base = GIC_DIST_BASE;
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if (irq < 16) {
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pr_info("Fail to enable interrupt %d\n", irq);
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return;
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}
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writel(mask, dist_base + GIC_DIST_ENABLE_SET + irq / 32 * 4);
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/* add memory barrier */
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mb();
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}
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/*
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* mt_irq_mask_for_sleep: disable an interrupt for the sleep manager's use
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* @irq: interrupt id
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* (THIS IS ONLY FOR SLEEP FUNCTION USE. DO NOT USE IT YOURSELF!)
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*/
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void mt_irq_mask_for_sleep(unsigned int virq)
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{
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u32 mask;
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void __iomem *dist_base;
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unsigned int irq = get_hardware_irq(virq);
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if (irq < 0)
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return;
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mask = 1 << (irq % 32);
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dist_base = GIC_DIST_BASE;
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if (irq < 16) {
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pr_info("Fail to enable interrupt %d\n", irq);
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return;
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}
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writel(mask, dist_base + GIC_DIST_ENABLE_CLEAR + irq / 32 * 4);
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/* add memory barrier */
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mb();
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}
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#if defined(CONFIG_FIQ_GLUE)
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#ifdef NR_IRQS
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#undef NR_IRQS
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#define NR_IRQS 224
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#else
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#define NR_IRQS 224
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#endif
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#define CPU_BRINGUP_SGI 1
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#define FIQ_DBG_SGI 14
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#define NR_GIC_SGI 16
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#define NR_GIC_PPI 16
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#define GIC_PRIVATE_SIGNALS 32
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#define MT_WDT_IRQ_ID 120
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struct irq2fiq {
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int irq;
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int count;
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fiq_isr_handler handler;
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void *arg;
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};
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struct fiq_isr_log {
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int in_fiq_isr;
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int irq;
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int smp_call_cnt;
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};
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#define line_fiq(no) (is_fiq_set[(no)/32] & (1<<((no)&31)))
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#define line_is_fiq(no) ((no) < NR_IRQS && line_fiq(no))
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#define line_set_fiq(no) \
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do { \
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if ((no) < NR_IRQS) \
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is_fiq_set[(no)/32] |= (1<<((no)&31)); \
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} while (0)
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static struct irq2fiq irqs_to_fiq[] = {
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{.irq = MT_WDT_IRQ_ID,},
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{.irq = FIQ_SMP_CALL_SGI,},
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};
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static struct fiq_isr_log fiq_isr_logs[NR_CPUS];
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static unsigned int is_fiq_set[(NR_IRQS + 31) / 32];
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static int fiq_glued;
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unsigned int irq_total_secondary_cpus;
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static spinlock_t irq_lock;
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/*
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* mt_irq_mask: disable an interrupt.
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* @data: irq_data
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*/
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static void mt_irq_mask(struct irq_data *data)
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{
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const unsigned int irq = data->irq;
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u32 mask = 1 << (irq % 32);
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if (irq < NR_GIC_SGI) {
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/*Note: workaround for false alarm*/
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if (irq != FIQ_DBG_SGI)
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pr_info("Fail to disable interrupt %d\n", irq);
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return;
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}
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writel(mask, (void *)(GIC_DIST_BASE + GIC_DIST_ENABLE_CLEAR
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+ irq / 32 * 4));
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dsb();
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}
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/*
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* mt_irq_unmask: enable an interrupt.
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* @data: irq_data
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*/
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static void mt_irq_unmask(struct irq_data *data)
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{
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const unsigned int irq = data->irq;
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u32 mask = 1 << (irq % 32);
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if (irq < NR_GIC_SGI) {
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/*Note: workaround for false alarm:*/
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if (irq != FIQ_DBG_SGI)
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pr_info("Fail to enable interrupt %d\n", irq);
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return;
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}
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writel(mask, (void *)(GIC_DIST_BASE + GIC_DIST_ENABLE_SET
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+ irq / 32 * 4));
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dsb();
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}
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/*
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* mt_irq_set_sens: set the interrupt sensitivity
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* @irq: interrupt id
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* @sens: sensitivity
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*/
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static void mt_irq_set_sens(unsigned int irq, unsigned int sens)
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{
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unsigned long flags;
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u32 config;
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if (irq < (NR_GIC_SGI + NR_GIC_PPI)) {
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pr_info("Fail to set sensitivity of interrupt %d\n", irq);
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return;
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}
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spin_lock_irqsave(&irq_lock, flags);
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if (sens == MT_EDGE_SENSITIVE) {
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config = readl((void *)(GIC_DIST_BASE + GIC_DIST_CONFIG
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+ (irq / 16) * 4));
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config |= (0x2 << (irq % 16) * 2);
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writel(config, (void *)(GIC_DIST_BASE + GIC_DIST_CONFIG
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+ (irq / 16) * 4));
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} else {
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config = readl((void *)(GIC_DIST_BASE + GIC_DIST_CONFIG
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+ (irq / 16) * 4));
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config &= ~(0x2 << (irq % 16) * 2);
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writel(config, (void *)(GIC_DIST_BASE + GIC_DIST_CONFIG
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+ (irq / 16) * 4));
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}
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spin_unlock_irqrestore(&irq_lock, flags);
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dsb();
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}
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/*
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* mt_irq_set_polarity: set the interrupt polarity
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* @irq: interrupt id
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* @polarity: interrupt polarity
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*/
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static void mt_irq_set_polarity(unsigned int irq, unsigned int polarity)
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{
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unsigned long flags;
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u32 offset, reg_index, value;
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if (irq < (NR_GIC_SGI + NR_GIC_PPI)) {
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pr_info("Fail to set polarity of interrupt %d\n", irq);
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return;
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}
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offset = (irq - GIC_PRIVATE_SIGNALS) & 0x1F;
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reg_index = (irq - GIC_PRIVATE_SIGNALS) >> 5;
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spin_lock_irqsave(&irq_lock, flags);
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if (polarity == 0) {
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/* active low */
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value = readl((void *)(INT_POL_CTL0 + (reg_index * 4)));
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value |= (1 << offset);
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writel(value, (INT_POL_CTL0 + (reg_index * 4)));
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} else {
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/* active high */
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value = readl((void *)(INT_POL_CTL0 + (reg_index * 4)));
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value &= ~(0x1 << offset);
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writel(value, INT_POL_CTL0 + (reg_index * 4));
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}
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dsb();
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spin_unlock_irqrestore(&irq_lock, flags);
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}
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/*
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* mt_irq_set_type: set interrupt type
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* @irq: interrupt id
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* @flow_type: interrupt type
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* Always return 0.
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*/
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static int mt_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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const unsigned int irq = data->irq;
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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mt_irq_set_sens(irq, MT_EDGE_SENSITIVE);
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mt_irq_set_polarity(irq, (flow_type & IRQF_TRIGGER_FALLING)
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? 0 : 1);
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__irq_set_handler_locked(irq, handle_edge_irq);
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} else if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
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mt_irq_set_sens(irq, MT_LEVEL_SENSITIVE);
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mt_irq_set_polarity(irq, (flow_type & IRQF_TRIGGER_LOW)
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? 0 : 1);
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__irq_set_handler_locked(irq, handle_level_irq);
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}
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return 0;
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}
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#ifdef CONFIG_MTK_IN_HOUSE_TEE_SUPPORT
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static inline void __mt_enable_fiq(int irq)
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{
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struct irq_data data;
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if (!line_is_fiq(irq)) {
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data.irq = irq;
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mt_irq_unmask(&data);
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return;
|
|
}
|
|
|
|
kree_enable_fiq(irq);
|
|
}
|
|
|
|
static inline void __mt_disable_fiq(int irq)
|
|
{
|
|
struct irq_data data;
|
|
|
|
if (!line_is_fiq(irq)) {
|
|
data.irq = irq;
|
|
mt_irq_mask(&data);
|
|
return;
|
|
}
|
|
|
|
kree_disable_fiq(irq);
|
|
}
|
|
|
|
static int mt_irq_set_fiq(int irq, unsigned long irq_flags)
|
|
{
|
|
struct irq_data data;
|
|
int ret;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&irq_lock, flags);
|
|
ret = kree_set_fiq(irq, irq_flags);
|
|
spin_unlock_irqrestore(&irq_lock, flags);
|
|
if (!ret) {
|
|
data.irq = irq;
|
|
mt_irq_set_type(&data, irq_flags);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static inline unsigned int mt_fiq_get_intack(void)
|
|
{
|
|
return kree_fiq_get_intack();
|
|
}
|
|
|
|
static inline void mt_fiq_eoi(unsigned int iar)
|
|
{
|
|
kree_fiq_eoi(iar);
|
|
}
|
|
|
|
static int irq_raise_softfiq(const struct cpumask *mask, unsigned int irq)
|
|
{
|
|
if (!line_is_fiq(irq))
|
|
return 0;
|
|
|
|
kree_raise_softfiq(*cpus_addr(*mask), irq);
|
|
return 1;
|
|
}
|
|
|
|
static int restore_for_fiq(struct notifier_block *nfb, unsigned long action,
|
|
void *hcpu)
|
|
{
|
|
/* Do nothing. TEE should recover GIC by itself */
|
|
return NOTIFY_OK;
|
|
}
|
|
#else
|
|
static void __set_security(int irq);
|
|
static void __raise_priority(int irq);
|
|
|
|
static inline void __mt_enable_fiq(int irq)
|
|
{
|
|
struct irq_data data;
|
|
|
|
data.irq = irq;
|
|
mt_irq_unmask(&data);
|
|
}
|
|
|
|
static inline void __mt_disable_fiq(int irq)
|
|
{
|
|
struct irq_data data;
|
|
|
|
data.irq = irq;
|
|
mt_irq_mask(&data);
|
|
}
|
|
|
|
static int mt_irq_set_fiq(int irq, unsigned long irq_flags)
|
|
{
|
|
struct irq_data data;
|
|
|
|
__set_security(irq);
|
|
__raise_priority(irq);
|
|
data.irq = irq;
|
|
mt_irq_set_type(&data, irq_flags);
|
|
return 0;
|
|
}
|
|
|
|
static inline unsigned int mt_fiq_get_intack(void)
|
|
{
|
|
return readl((void *)(GIC_CPU_BASE + GIC_CPU_INTACK));
|
|
}
|
|
|
|
static inline void mt_fiq_eoi(unsigned int iar)
|
|
{
|
|
writel(iar, (void *)(GIC_CPU_BASE + GIC_CPU_EOI));
|
|
dsb();
|
|
}
|
|
|
|
/* No TEE, just let kernel gic send it. */
|
|
static int irq_raise_softfiq(const struct cpumask *mask, unsigned int irq)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void __set_security(int irq)
|
|
{
|
|
u32 val;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&irq_lock, flags);
|
|
|
|
val = readl((void *)(GIC_ICDISR + 4 * (irq / 32)));
|
|
val &= ~(1 << (irq % 32));
|
|
writel(val, (void *)(GIC_ICDISR + 4 * (irq / 32)));
|
|
|
|
spin_unlock_irqrestore(&irq_lock, flags);
|
|
}
|
|
|
|
static void __raise_priority(int irq)
|
|
{
|
|
u32 val;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&irq_lock, flags);
|
|
|
|
val = readl((void *)(GIC_DIST_BASE + GIC_DIST_PRI + 4 * (irq / 4)));
|
|
val &= ~(0xFF << ((irq % 4) * 8));
|
|
val |= (0x50 << ((irq % 4) * 8));
|
|
writel(val, (void *)(GIC_DIST_BASE + GIC_DIST_PRI + 4 * (irq / 4)));
|
|
|
|
spin_unlock_irqrestore(&irq_lock, flags);
|
|
}
|
|
|
|
static int restore_for_fiq(struct notifier_block *nfb, unsigned long action,
|
|
void *hcpu)
|
|
{
|
|
int i;
|
|
|
|
switch (action) {
|
|
case CPU_STARTING:
|
|
for (i = 0; i < ARRAY_SIZE(irqs_to_fiq); i++) {
|
|
if ((irqs_to_fiq[i].irq < (NR_GIC_SGI + NR_GIC_PPI))
|
|
&& (irqs_to_fiq[i].handler)) {
|
|
__set_security(irqs_to_fiq[i].irq);
|
|
__raise_priority(irqs_to_fiq[i].irq);
|
|
dsb();
|
|
}
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
#endif /* CONFIG_MTK_IN_HOUSE_TEE_SUPPORT */
|
|
|
|
/*
|
|
* trigger_sw_irq: force to trigger a GIC SGI.
|
|
* @irq: SGI number
|
|
*/
|
|
void trigger_sw_irq(int irq)
|
|
{
|
|
if (irq < NR_GIC_SGI)
|
|
writel((0x18000 | irq), (void *)(GIC_DIST_BASE
|
|
+ GIC_DIST_SOFTINT));
|
|
}
|
|
|
|
/*
|
|
* mt_disable_fiq: disable an interrupt which is directed to FIQ.
|
|
* @irq: interrupt id
|
|
* Return error code.
|
|
* NoteXXX: Not allow to suspend due to FIQ context.
|
|
*/
|
|
int mt_disable_fiq(int irq)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(irqs_to_fiq); i++) {
|
|
if (irqs_to_fiq[i].irq == irq) {
|
|
__mt_disable_fiq(irq);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* mt_enable_fiq: enable an interrupt which is directed to FIQ.
|
|
* @irq: interrupt id
|
|
* Return error code.
|
|
* NoteXXX: Not allow to suspend due to FIQ context.
|
|
*/
|
|
int mt_enable_fiq(int irq)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(irqs_to_fiq); i++) {
|
|
if (irqs_to_fiq[i].irq == irq) {
|
|
__mt_enable_fiq(irq);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* For gic_arch_extn, check and mask if it is FIQ.
|
|
*/
|
|
static void mt_fiq_mask_check(struct irq_data *d)
|
|
{
|
|
if (!line_is_fiq(d->irq))
|
|
return;
|
|
|
|
__mt_disable_fiq(d->irq);
|
|
}
|
|
|
|
/*
|
|
* For gic_arch_extn, check and unmask if it is FIQ.
|
|
*/
|
|
static void mt_fiq_unmask_check(struct irq_data *d)
|
|
{
|
|
if (!line_is_fiq(d->irq))
|
|
return;
|
|
|
|
__mt_enable_fiq(d->irq);
|
|
}
|
|
|
|
/*
|
|
* fiq_isr: FIQ handler.
|
|
*/
|
|
static void fiq_isr(struct fiq_glue_handler *h, void *regs, void *svc_sp)
|
|
{
|
|
unsigned int iar, irq;
|
|
int i;
|
|
|
|
iar = mt_fiq_get_intack();
|
|
irq = iar & 0x3FF;
|
|
|
|
if (irq >= NR_IRQS)
|
|
return;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(irqs_to_fiq); i++) {
|
|
if (irqs_to_fiq[i].irq == irq) {
|
|
if (irqs_to_fiq[i].handler) {
|
|
irqs_to_fiq[i].count++;
|
|
(irqs_to_fiq[i].handler) (irqs_to_fiq[i].arg,
|
|
regs, svc_sp);
|
|
} else {
|
|
pr_info("Unexpected interrupt %d received!\n",
|
|
irq);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
if (i == ARRAY_SIZE(irqs_to_fiq))
|
|
pr_info("Interrupt %d triggers FIQ but it is not registered\n",
|
|
irq);
|
|
|
|
mt_fiq_eoi(iar);
|
|
}
|
|
|
|
/*
|
|
* get_fiq_isr_log: get fiq_isr_log for debugging.
|
|
* @cpu: processor id
|
|
* @log: pointer to the address of fiq_isr_log
|
|
* @len: length of fiq_isr_log
|
|
* Return 0 for success or error code for failure.
|
|
*/
|
|
int get_fiq_isr_log(int cpu, unsigned int *log, unsigned int *len)
|
|
{
|
|
if (log)
|
|
*log = (unsigned int)&(fiq_isr_logs[cpu]);
|
|
|
|
if (len)
|
|
*len = sizeof(struct fiq_isr_log);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct notifier_block fiq_notifier = {
|
|
.notifier_call = restore_for_fiq,
|
|
};
|
|
|
|
static struct fiq_glue_handler fiq_handler = {
|
|
.fiq = fiq_isr,
|
|
};
|
|
|
|
static int __init_fiq(void)
|
|
{
|
|
int ret;
|
|
|
|
spin_lock_init(&irq_lock);
|
|
register_cpu_notifier(&fiq_notifier);
|
|
irq_total_secondary_cpus = num_possible_cpus() - 1;
|
|
|
|
/* Hook FIQ checker for mask/unmask. */
|
|
/* So kernel enable_irq/disable_irq call will set FIQ correctly. */
|
|
/* This is necessary for IRQ/FIQ suspend to work. */
|
|
gic_arch_extn.irq_mask = mt_fiq_mask_check;
|
|
gic_arch_extn.irq_unmask = mt_fiq_unmask_check;
|
|
|
|
ret = fiq_glue_register_handler(&fiq_handler);
|
|
if (ret)
|
|
pr_info("fail to register fiq_glue_handler\n");
|
|
else
|
|
fiq_glued = 1;
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* request_fiq: direct an interrupt to FIQ and register its handler.
|
|
* @irq: interrupt id
|
|
* @handler: FIQ handler
|
|
* @irq_flags: IRQF_xxx
|
|
* @arg: argument to the FIQ handler
|
|
* Return error code.
|
|
*/
|
|
int request_fiq(int irq, fiq_isr_handler handler, unsigned long irq_flags,
|
|
void *arg)
|
|
{
|
|
int i;
|
|
unsigned long flags;
|
|
|
|
if (!fiq_glued)
|
|
__init_fiq();
|
|
|
|
for (i = 0; i < ARRAY_SIZE(irqs_to_fiq); i++) {
|
|
spin_lock_irqsave(&irq_lock, flags);
|
|
|
|
if (irqs_to_fiq[i].irq == irq) {
|
|
irqs_to_fiq[i].handler = handler;
|
|
irqs_to_fiq[i].arg = arg;
|
|
|
|
line_set_fiq(irq);
|
|
spin_unlock_irqrestore(&irq_lock, flags);
|
|
if (mt_irq_set_fiq(irq, irq_flags))
|
|
break;
|
|
|
|
/* add memory barrier */
|
|
mb();
|
|
__mt_enable_fiq(irq);
|
|
return 0;
|
|
}
|
|
spin_unlock_irqrestore(&irq_lock, flags);
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
|
|
void irq_raise_softirq(const struct cpumask *mask, unsigned int irq)
|
|
{
|
|
unsigned long map = *cpus_addr(*mask);
|
|
int satt, cpu, cpu_bmask;
|
|
u32 val;
|
|
|
|
satt = 1 << 15;
|
|
/*
|
|
* NoteXXX: CPU1 SGI is configured as secure as default.
|
|
* Need to use the secure SGI 1 which is for waking up cpu1.
|
|
*/
|
|
if (irq == CPU_BRINGUP_SGI) {
|
|
if (irq_total_secondary_cpus) {
|
|
--irq_total_secondary_cpus;
|
|
satt = 0;
|
|
}
|
|
}
|
|
|
|
val = readl(IOMEM(GIC_DIST_BASE + GIC_DIST_IGROUP + 4 * (irq / 32)));
|
|
if (!(val & (1 << (irq % 32)))) { /* secure interrupt? */
|
|
satt = 0;
|
|
}
|
|
|
|
cpu = 0;
|
|
cpu_bmask = 0;
|
|
|
|
#if defined(SPM_MCDI_FUNC)
|
|
/*
|
|
* Processors cannot receive interrupts during power-down.
|
|
* Wait until the SPM checks status and returns.
|
|
*/
|
|
for_each_cpu(cpu, mask) {
|
|
cpu_bmask |= 1 << cpu;
|
|
}
|
|
spm_check_core_status_before(cpu_bmask);
|
|
#endif
|
|
|
|
if (irq_raise_softfiq(mask, irq) == 0) {
|
|
/*
|
|
* Ensure that stores to Normal memory are visible to the
|
|
* other CPUs before issuing the IPI.
|
|
*/
|
|
dsb();
|
|
writel(((map << 16) | satt | irq), (void *)(GIC_DIST_BASE
|
|
+ GIC_DIST_SOFTINT));
|
|
dsb();
|
|
}
|
|
|
|
#if defined(SPM_MCDI_FUNC)
|
|
spm_check_core_status_after(cpu_bmask);
|
|
#endif
|
|
|
|
}
|
|
#else
|
|
int get_fiq_isr_log(int cpu, unsigned int *log, unsigned int *len)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
|
|
int request_fiq(int irq, fiq_isr_handler handler, unsigned long irq_flags,
|
|
void *arg)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
|
|
#endif /* CONFIG_FIQ_GLUE */
|
|
|
|
static int __init mtk_gic_ext_init(void)
|
|
{
|
|
struct device_node *node;
|
|
|
|
node = of_find_compatible_node(NULL, NULL, "arm,gic-400");
|
|
if (!node) {
|
|
node = of_find_compatible_node(NULL, NULL, "arm,cortex-a7-gic");
|
|
if (!node) {
|
|
pr_info("[gic_ext] find arm,gic node failed\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
GIC_DIST_BASE = of_iomap(node, 0);
|
|
if (IS_ERR(GIC_DIST_BASE))
|
|
return -EINVAL;
|
|
|
|
GIC_CPU_BASE = of_iomap(node, 1);
|
|
if (IS_ERR(GIC_CPU_BASE))
|
|
return -EINVAL;
|
|
node = of_find_compatible_node(NULL, NULL, "mediatek,mt6577-sysirq");
|
|
if (!node) {
|
|
pr_info("[gic_ext] find mediatek,mt6577-sysirq node failed\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
INT_POL_CTL0 = of_iomap(node, 0);
|
|
if (IS_ERR(INT_POL_CTL0))
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
arch_initcall(mtk_gic_ext_init);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("MediaTek gic extend Driver");
|
|
MODULE_AUTHOR("Maoguang Meng <maoguang.meng@mediatek.com>");
|