208 lines
5.6 KiB
C
208 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2021 MediaTek Inc.
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*/
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#ifndef _bq24296_SW_H_
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#define _bq24296_SW_H_
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#define bq24296_CON0 0x00
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#define bq24296_CON1 0x01
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#define bq24296_CON2 0x02
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#define bq24296_CON3 0x03
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#define bq24296_CON4 0x04
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#define bq24296_CON5 0x05
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#define bq24296_CON6 0x06
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#define bq24296_CON7 0x07
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#define bq24296_CON8 0x08
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#define bq24296_CON9 0x09
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#define bq24296_CON10 0x0A
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/**********************************************************
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*
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* [MASK/SHIFT]
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*
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*********************************************************/
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/*CON0*/
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#define CON0_EN_HIZ_MASK 0x01
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#define CON0_EN_HIZ_SHIFT 7
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#define CON0_VINDPM_MASK 0x0F
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#define CON0_VINDPM_SHIFT 3
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#define CON0_IINLIM_MASK 0x07
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#define CON0_IINLIM_SHIFT 0
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/*CON1*/
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#define CON1_REG_RST_MASK 0x01
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#define CON1_REG_RST_SHIFT 7
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#define CON1_WDT_RST_MASK 0x01
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#define CON1_WDT_RST_SHIFT 6
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#define CON1_OTG_CONFIG_MASK 0x01
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#define CON1_OTG_CONFIG_SHIFT 5
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#define CON1_CHG_CONFIG_MASK 0x01
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#define CON1_CHG_CONFIG_SHIFT 4
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#define CON1_SYS_MIN_MASK 0x07
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#define CON1_SYS_MIN_SHIFT 1
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#define CON1_BOOST_LIM_MASK 0x01
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#define CON1_BOOST_LIM_SHIFT 0
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/*CON2*/
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#define CON2_ICHG_MASK 0x3F
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#define CON2_ICHG_SHIFT 2
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#define CON2_BCOLD_MASK 0x1
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#define CON2_BCOLD_SHIFT 1
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#define CON2_FORCE_20PCT_MASK 0x1
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#define CON2_FORCE_20PCT_SHIFT 0
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/*CON3*/
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#define CON3_IPRECHG_MASK 0x0F
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#define CON3_IPRECHG_SHIFT 4
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#define CON3_ITERM_MASK 0x0F
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#define CON3_ITERM_SHIFT 0
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/*CON4*/
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#define CON4_VREG_MASK 0x3F
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#define CON4_VREG_SHIFT 2
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#define CON4_BATLOWV_MASK 0x01
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#define CON4_BATLOWV_SHIFT 1
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#define CON4_VRECHG_MASK 0x01
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#define CON4_VRECHG_SHIFT 0
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/*CON5*/
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#define CON5_EN_TERM_MASK 0x01
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#define CON5_EN_TERM_SHIFT 7
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#define CON5_WATCHDOG_MASK 0x03
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#define CON5_WATCHDOG_SHIFT 4
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#define CON5_EN_TIMER_MASK 0x01
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#define CON5_EN_TIMER_SHIFT 3
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#define CON5_CHG_TIMER_MASK 0x03
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#define CON5_CHG_TIMER_SHIFT 1
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/*CON6*/
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#define CON6_BOOSTV_MASK 0xF
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#define CON6_BOOSTV_SHIFT 4
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#define CON6_BHOT_MASK 0x3
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#define CON6_BHOT_SHIFT 2
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#define CON6_TREG_MASK 0x03
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#define CON6_TREG_SHIFT 0
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/*CON7*/
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#define CON7_TMR2X_EN_MASK 0x01
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#define CON7_TMR2X_EN_SHIFT 6
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#define CON7_BATFET_Disable_MASK 0x01
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#define CON7_BATFET_Disable_SHIFT 5
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#define CON7_INT_MASK_MASK 0x03
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#define CON7_INT_MASK_SHIFT 0
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/*CON8*/
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#define CON8_VBUS_STAT_MASK 0x03
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#define CON8_VBUS_STAT_SHIFT 6
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#define CON8_CHRG_STAT_MASK 0x03
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#define CON8_CHRG_STAT_SHIFT 4
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#define CON8_DPM_STAT_MASK 0x01
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#define CON8_DPM_STAT_SHIFT 3
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#define CON8_PG_STAT_MASK 0x01
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#define CON8_PG_STAT_SHIFT 2
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#define CON8_THERM_STAT_MASK 0x01
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#define CON8_THERM_STAT_SHIFT 1
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#define CON8_VSYS_STAT_MASK 0x01
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#define CON8_VSYS_STAT_SHIFT 0
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/*CON9*/
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#define CON9_WATCHDOG_FAULT_MASK 0x01
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#define CON9_WATCHDOG_FAULT_SHIFT 7
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#define CON9_OTG_FAULT_MASK 0x01
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#define CON9_OTG_FAULT_SHIFT 6
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#define CON9_CHRG_FAULT_MASK 0x03
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#define CON9_CHRG_FAULT_SHIFT 4
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#define CON9_BAT_FAULT_MASK 0x01
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#define CON9_BAT_FAULT_SHIFT 3
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#define CON9_NTC_FAULT_MASK 0x07
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#define CON9_NTC_FAULT_SHIFT 0
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/*CON10*/
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#define CON10_PN_MASK 0x07
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#define CON10_PN_SHIFT 3
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#define CON10_Rev_MASK 0x07
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#define CON10_Rev_SHIFT 0
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/**********************************************************
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*
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*[Extern Function]
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*
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*********************************************************/
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/*CON0----------------------------------------------------*/
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extern void bq24296_set_en_hiz(unsigned int val);
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extern void bq24296_set_vindpm(unsigned int val);
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extern void bq24296_set_iinlim(unsigned int val);
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/*CON1----------------------------------------------------*/
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extern void bq24296_set_reg_rst(unsigned int val);
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extern void bq24296_set_wdt_rst(unsigned int val);
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extern void bq24296_set_chg_config(unsigned int val);
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extern void bq24296_set_otg_config(unsigned int val);
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extern void bq24296_set_sys_min(unsigned int val);
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extern void bq24296_set_boost_lim(unsigned int val);
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/*CON2----------------------------------------------------*/
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extern void bq24296_set_ichg(unsigned int val);
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extern void bq24296_set_bcold(unsigned int val);
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extern void bq24296_set_force_20pct(unsigned int val);
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/*CON3----------------------------------------------------*/
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extern void bq24296_set_iprechg(unsigned int val);
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extern void bq24296_set_iterm(unsigned int val);
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/*CON4----------------------------------------------------*/
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extern void bq24296_set_vreg(unsigned int val);
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extern void bq24296_set_batlowv(unsigned int val);
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extern void bq24296_set_vrechg(unsigned int val);
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/*CON5----------------------------------------------------*/
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extern void bq24296_set_en_term(unsigned int val);
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extern void bq24296_set_watchdog(unsigned int val);
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extern void bq24296_set_en_timer(unsigned int val);
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extern void bq24296_set_chg_timer(unsigned int val);
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/*CON6----------------------------------------------------*/
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extern void bq24296_set_treg(unsigned int val);
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extern void bq24296_set_boostv(unsigned int val);
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extern void bq24296_set_bhot(unsigned int val);
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/*CON7----------------------------------------------------*/
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extern void bq24296_set_tmr2x_en(unsigned int val);
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extern void bq24296_set_batfet_disable(unsigned int val);
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extern void bq24296_set_int_mask(unsigned int val);
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/*CON8----------------------------------------------------*/
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extern unsigned int bq24296_get_system_status(void);
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extern unsigned int bq24296_get_vbus_stat(void);
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extern unsigned int bq24296_get_chrg_stat(void);
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extern unsigned int bq24296_get_vsys_stat(void);
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/*---------------------------------------------------------*/
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extern void bq24296_dump_register(void);
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extern unsigned int bq24296_read_interface(unsigned char RegNum,
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unsigned char *val,
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unsigned char MASK,
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unsigned char SHIFT);
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#endif /* _bq24296_SW_H_*/
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