90 lines
1.6 KiB
C
90 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_QOS_IPI_H__
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#define __MTK_QOS_IPI_H__
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struct qos_ipi_cmd {
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int id;
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bool valid;
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};
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enum {
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QOS_IPI_QOS_ENABLE,
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QOS_IPI_SWPM_INIT,
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QOS_IPI_UPOWER_DATA_TRANSFER,
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QOS_IPI_UPOWER_DUMP_TABLE,
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QOS_IPI_GET_GPU_BW,
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QOS_IPI_SWPM_ENABLE,
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QOS_IPI_QOS_BOUND,
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QOS_IPI_QOS_BOUND_ENABLE,
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QOS_IPI_QOS_BOUND_STRESS_ENABLE,
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QOS_IPI_SMI_MET_MON,
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QOS_IPI_SETUP_GPU_INFO,
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QOS_IPI_SWPM_SET_UPDATE_CNT,
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};
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struct qos_ipi_data {
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unsigned int cmd;
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union {
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struct {
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unsigned int dvfsrc_en;
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unsigned int dram_type;
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} dvfsrc_enable;
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struct {
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unsigned int vcore_dvfs_opp;
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unsigned int vcore_uv;
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unsigned int ddr_khz;
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} opp_table;
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struct {
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unsigned int vcore_dvfs_opp;
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unsigned int vcore_opp;
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} vcore_opp;
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struct {
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unsigned int vcore_dvfs_opp;
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unsigned int ddr_opp;
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} ddr_opp;
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struct {
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unsigned int dram_addr;
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unsigned int dram_size;
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unsigned int dram_ch_num;
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} swpm_init;
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struct {
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unsigned int type;
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unsigned int enable;
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} swpm_enable;
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struct {
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unsigned int type;
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unsigned int cnt;
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} swpm_set_update_cnt;
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struct {
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unsigned int arg[3];
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} upower_data;
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struct {
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unsigned int state;
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} qos_bound;
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struct {
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unsigned int enable;
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} qos_bound_enable;
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struct {
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unsigned int enable;
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} qos_bound_stress_enable;
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struct {
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unsigned int ena;
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unsigned int enc[4];
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} smi_met_mon;
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struct {
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unsigned int addr;
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unsigned int addr_hi;
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unsigned int size;
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} gpu_info;
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} u;
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};
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extern int qos_ipi_to_sspm_command(void *buffer, int slot);
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#endif
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