515 lines
17 KiB
C
515 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017 MediaTek Inc.
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*/
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#ifndef _MTK_QMU_H_
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#define _MTK_QMU_H_
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#ifdef CONFIG_MTK_MUSB_QMU_SUPPORT
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/* for musb_read/write api */
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#include "mtk_musb.h"
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#include "musb_debug.h"
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#include "musb_io.h"
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#include <linux/dmapool.h>
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/* CUSTOM SETTING */
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#define GPD_LEN_ALIGNED (64) /* > gpd len (16) and cache line size aligned */
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/* GPD_LEN_ALIGNED -
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* 16(should be sizeof(TGPD)
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*/
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#define GPD_EXT_LEN (48)
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#define GPD_SZ (16)
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#define DFT_MAX_GPD_NUM 144
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#ifndef MUSB_QMU_LIMIT_SUPPORT
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#define RXQ_NUM 8
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#define TXQ_NUM 8
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#else
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#define RXQ_NUM MUSB_QMU_LIMIT_RXQ_NUM
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#define TXQ_NUM MUSB_QMU_LIMIT_TXQ_NUM
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#endif
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#define MAX_QMU_EP RXQ_NUM
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#define TXQ 0
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#define RXQ 1
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#define ISOC_EP_START_IDX 1
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/* QMU SETTING */
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#define NO_ZLP 0
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#define HW_MODE 1
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#define GPD_MODE 2
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#define TXZLP GPD_MODE
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/* #define TXZLP HW_MODE */
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/*#define TXZLP NO_ZLP */
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/* #define CFG_RX_ZLP_EN */
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#define CFG_RX_COZ_EN
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#define CFG_CS_CHECK
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/* #define CFG_EMPTY_CHECK */
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#ifdef CONFIG_MTK_MUSB_DRV_36BIT
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struct tx_haddr {
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u8 hiaddr;
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u8 reserved;
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};
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struct rx_haddr {
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u8 hiaddr;
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};
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union gpd_b14 {
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u8 ExtLength; /*Tx ExtLength for TXGPD*/
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struct rx_haddr rx_haddr; /*Rx hi address for RXGPD*/
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};
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union gpd_w1 {
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u16 DataBufferLen; /*Rx Allow Length for RXGPD*/
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struct tx_haddr tx_haddr; /*Tx hi address for TXGPD */
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};
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#endif
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/* TGPD */
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struct TGPD {
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u8 flag;
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u8 chksum;
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#ifdef CONFIG_MTK_MUSB_DRV_36BIT
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union gpd_w1 gpd_w1;
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#else
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u16 DataBufferLen; /*Rx Allow Length */
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#endif
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/* address field, 32-bit long */
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u32 pNext;
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u32 pBuf;
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u16 bufLen;
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#ifdef CONFIG_MTK_MUSB_DRV_36BIT
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union gpd_b14 gpd_b14;
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#else
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u8 ExtLength;
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#endif
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u8 ZTepFlag;
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};
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struct _GPD_RANGE {
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struct TGPD *pNext;
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struct TGPD *pStart;
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struct TGPD *pEnd;
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};
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extern int mtk_host_qmu_concurrent;
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extern int mtk_host_qmu_pipe_msk;
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extern int mtk_host_qmu_force_isoc_restart;
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extern int mtk_host_active_dev_cnt;
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#ifdef CONFIG_MTK_UAC_POWER_SAVING
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extern unsigned int low_power_timer_total_trigger_cnt;
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extern unsigned int low_power_timer_total_wake_cnt;
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extern int low_power_timer_mode2_option;
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extern int low_power_timer_mode;
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extern int usb_on_sram;
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extern int audio_on_sram;
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extern int use_mtk_audio;
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extern int mtk_audio_request_sram
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(dma_addr_t *phys_addr, unsigned char **virt_addr,
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unsigned int length, void *user);
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extern void mtk_audio_free_sram(void *user);
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extern int gpd_switch_to_sram(struct device *dev);
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extern void gpd_switch_to_dram(struct device *dev);
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#endif
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extern int mtk_qmu_dbg_level; /* refer to musb_core.c */
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extern int mtk_qmu_max_gpd_num;
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extern int isoc_ep_end_idx;
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extern int isoc_ep_gpd_count;
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static inline int mtk_dbg_level(unsigned int level)
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{
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return mtk_qmu_dbg_level >= level;
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}
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#define LOG_EMERG 0
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#define LOG_ALERT 1
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#define LOG_CRIT 2
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#define LOG_ERR 3
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#define LOG_WARN 4
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#define LOG_NOTICE 5
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#define LOG_INFO 6
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#define LOG_DBG 7
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#define QMU_DBG_ON
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#ifdef QMU_DBG_ON
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#define QMU_ERR(format, args...) do {if (mtk_dbg_level(LOG_ERR)) \
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pr_notice("QMU_ERR,<%s %d>, " format, __func__, __LINE__, ## args); } \
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while (0)
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#define QMU_WARN(format, args...) do {if (mtk_dbg_level(LOG_WARN)) \
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pr_notice("QMU_WARN,<%s %d>, " format, __func__, __LINE__, ## args); } \
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while (0)
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#define QMU_INFO(format, args...) do {if (mtk_dbg_level(LOG_INFO)) \
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pr_notice("QMU_INFO,<%s %d>, " format, __func__, __LINE__, ## args); } \
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while (0)
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#define QMU_DBG(format, args...) do {if (mtk_dbg_level(LOG_DBG)) \
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pr_notice("QMU_DBG,<%s %d>, " format, __func__, __LINE__, ## args); } \
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while (0)
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#else
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#define QMU_ERR(format, args...) do {} while (0)
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#define QMU_WARN(format, args...) do {} while (0)
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#define QMU_INFO(format, args...) do {} while (0)
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#define QMU_DBG(format, args...) do {} while (0)
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#endif
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/* QMU macros */
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#define USB_HW_QMU_OFF 0x0000
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#define USB_HW_QUCS_OFF 0x0300
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#define USB_HW_QIRQ_OFF 0x0400
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#define USB_HW_QDBG_OFF 0x04F0
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#define MGC_O_QMU_QCR0 0x0000
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#define MGC_O_QMU_QCR2 0x0008
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#define MGC_O_QMU_QCR3 0x000C
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#define MGC_O_QMU_RQCSR0 0x0010
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#define MGC_O_QMU_RQSAR0 0x0014
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#define MGC_O_QMU_RQCPR0 0x0018
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#define MGC_O_QMU_RQCSR(n) (MGC_O_QMU_RQCSR0+0x0010*((n)-1))
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#define MGC_O_QMU_RQSAR(n) (MGC_O_QMU_RQSAR0+0x0010*((n)-1))
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#define MGC_O_QMU_RQCPR(n) (MGC_O_QMU_RQCPR0+0x0010*((n)-1))
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#define MGC_O_QMU_RQTR_BASE 0x0090
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#define MGC_O_QMU_RQTR(n) (MGC_O_QMU_RQTR_BASE+0x4*((n)-1))
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#define MGC_O_QMU_RQLDPR0 0x0100
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#define MGC_O_QMU_RQLDPR(n) (MGC_O_QMU_RQLDPR0+0x4*((n)-1))
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#define MGC_O_QMU_TQCSR0 0x0200
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#define MGC_O_QMU_TQSAR0 0x0204
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#define MGC_O_QMU_TQCPR0 0x0208
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#define MGC_O_QMU_TQCSR(n) (MGC_O_QMU_TQCSR0+0x0010*((n)-1))
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#define MGC_O_QMU_TQSAR(n) (MGC_O_QMU_TQSAR0+0x0010*((n)-1))
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#define MGC_O_QMU_TQCPR(n) (MGC_O_QMU_TQCPR0+0x0010*((n)-1))
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#define MGC_O_QMU_QAR 0x0300
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#define MGC_O_QUCS_USBGCSR 0x0000
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#define MGC_O_QIRQ_QISAR 0x0000
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#define MGC_O_QIRQ_QIMR 0x0004
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#define MGC_O_QIRQ_QIMCR 0x0008
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#define MGC_O_QIRQ_QIMSR 0x000C
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#define MGC_O_QIRQ_IOCDISR 0x0030
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#define MGC_O_QIRQ_TEPEMPR 0x0060
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#define MGC_O_QIRQ_TEPEMPMR 0x0064
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#define MGC_O_QIRQ_TEPEMPMCR 0x0068
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#define MGC_O_QIRQ_TEPEMPMSR 0x006C
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#define MGC_O_QIRQ_REPEMPR 0x0070
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#define MGC_O_QIRQ_REPEMPMR 0x0074
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#define MGC_O_QIRQ_REPEMPMCR 0x0078
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#define MGC_O_QIRQ_REPEMPMSR 0x007C
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#define MGC_O_QIRQ_RQEIR 0x0090
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#define MGC_O_QIRQ_RQEIMR 0x0094
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#define MGC_O_QIRQ_RQEIMCR 0x0098
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#define MGC_O_QIRQ_RQEIMSR 0x009C
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#define MGC_O_QIRQ_REPEIR 0x00A0
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#define MGC_O_QIRQ_REPEIMR 0x00A4
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#define MGC_O_QIRQ_REPEIMCR 0x00A8
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#define MGC_O_QIRQ_REPEIMSR 0x00AC
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#define MGC_O_QIRQ_TQEIR 0x00B0
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#define MGC_O_QIRQ_TQEIMR 0x00B4
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#define MGC_O_QIRQ_TQEIMCR 0x00B8
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#define MGC_O_QIRQ_TQEIMSR 0x00BC
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#define MGC_O_QIRQ_TEPEIR 0x00C0
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#define MGC_O_QIRQ_TEPEIMR 0x00C4
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#define MGC_O_QIRQ_TEPEIMCR 0x00C8
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#define MGC_O_QIRQ_TEPEIMSR 0x00CC
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#define MGC_O_QDBG_DFCR 0x0000
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#define MGC_O_QDBG_DFMR 0x0004
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/* brief Queue Control value Definition */
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#define DQMU_QUE_START 0x00000001
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#define DQMU_QUE_RESUME 0x00000002
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#define DQMU_QUE_STOP 0x00000004
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#define DQMU_QUE_ACTIVE 0x00008000
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/*brief USB QMU Special Control USBGCSR value Definition*/
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#define USB_QMU_Tx0_EN 0x00000001
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#define USB_QMU_Tx_EN(n) (USB_QMU_Tx0_EN<<((n)-1))
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#define USB_QMU_Rx0_EN 0x00010000
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#define USB_QMU_Rx_EN(n) (USB_QMU_Rx0_EN<<((n)-1))
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#define USB_QMU_HIFEVT_EN 0x00000100
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#define USB_QMU_HIFCMD_EN 0x01000000
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#define DQMU_SW_RESET 0x00010000
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#define DQMU_CS16B_EN 0x80000000
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#define DQMU_TQ0CS_EN 0x00010000
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#define DQMU_TQCS_EN(n) (DQMU_TQ0CS_EN<<((n)-1))
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#define DQMU_RQ0CS_EN 0x00000001
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#define DQMU_RQCS_EN(n) (DQMU_RQ0CS_EN<<((n)-1))
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#define DQMU_TX0_ZLP 0x01000000
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#define DQMU_TX_ZLP(n) (DQMU_TX0_ZLP<<((n)-1))
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#define DQMU_TX0_MULTIPLE 0x00010000
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#define DQMU_TX_MULTIPLE(n) (DQMU_TX0_MULTIPLE<<((n)-1))
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#define DQMU_T0Q_GDP_ZLP 0x00000100
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#define DQMU_TQ_GDP_ZLP(n) (DQMU_T0Q_GDP_ZLP<<((n)-1))
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#define DQMU_RX0_MULTIPLE 0x00010000
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#define DQMU_RX_MULTIPLE(n) (DQMU_RX0_MULTIPLE<<((n)-1))
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#define DQMU_RX0_ZLP 0x01000000
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#define DQMU_RX_ZLP(n) (DQMU_RX0_ZLP<<((n)-1))
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#define DQMU_RX0_COZ 0x00000100
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#define DQMU_RX_COZ(n) (DQMU_RX0_COZ<<((n)-1))
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#define DQMU_M_TXEP_ERR 0x10000000
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#define DQMU_M_TXQ_ERR 0x08000000
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#define DQMU_M_RXEP_ERR 0x04000000
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#define DQMU_M_RXQ_ERR 0x02000000
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#define DQMU_M_RQ_EMPTY 0x00020000
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#define DQMU_M_TQ_EMPTY 0x00010000
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#define DQMU_M_RX0_EMPTY 0x00000001
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#define DQMU_M_RX_EMPTY(n) (DQMU_M_RX0_EMPTY<<((n)-1))
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#define DQMU_M_TX0_EMPTY 0x00000001
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#define DQMU_M_TX_EMPTY(n) (DQMU_M_TX0_EMPTY<<((n)-1))
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#define DQMU_M_RX0_DONE 0x00000100
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#define DQMU_M_RX_DONE(n) (DQMU_M_RX0_DONE<<((n)-1))
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#define DQMU_M_TX0_DONE 0x00000001
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#define DQMU_M_TX_DONE(n) (DQMU_M_TX0_DONE<<((n)-1))
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#define DQMU_M_RX0_ZLP_ERR 0x01000000
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#define DQMU_M_RX_ZLP_ERR(n) (DQMU_M_RX0_ZLP_ERR<<((n)-1))
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#define DQMU_M_RX0_LEN_ERR 0x00000100
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#define DQMU_M_RX_LEN_ERR(n) (DQMU_M_RX0_LEN_ERR<<((n)-1))
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#define DQMU_M_RX0_GPDCS_ERR 0x00000001
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#define DQMU_M_RX_GPDCS_ERR(n) (DQMU_M_RX0_GPDCS_ERR<<((n)-1))
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#define DQMU_M_TX0_LEN_ERR 0x00010000
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#define DQMU_M_TX_LEN_ERR(n) (DQMU_M_TX0_LEN_ERR<<((n)-1))
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#define DQMU_M_TX0_GPDCS_ERR 0x00000100
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#define DQMU_M_TX_GPDCS_ERR(n) (DQMU_M_TX0_GPDCS_ERR<<((n)-1))
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#define DQMU_M_TX0_BDCS_ERR 0x00000001
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#define DQMU_M_TX_BDCS_ERR(n) (DQMU_M_TX0_BDCS_ERR<<((n)-1))
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#define DQMU_M_TX0_EP_ERR 0x00000001
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#define DQMU_M_TX_EP_ERR(n) (DQMU_M_TX0_EP_ERR<<((n)-1))
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#define DQMU_M_RX0_EP_ERR 0x00000001
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#define DQMU_M_RX_EP_ERR(n) (DQMU_M_RX0_EP_ERR<<((n)-1))
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#define DQMU_M_RQ_DIS_IOC(n) (0x100<<((n)-1))
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#define MGC_ReadQMU8(base, _offset) \
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musb_readb(base, (USB_HW_QMU_OFF + _offset))
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#define MGC_ReadQUCS8(base, _offset) \
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musb_readb(base, (USB_HW_QUCS_OFF + _offset))
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#define MGC_ReadQIRQ8(base, _offset) \
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musb_readb(base, (USB_HW_QIRQ_OFF + _offset))
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#define MGC_ReadQMU16(base, _offset) \
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musb_readw(base, (USB_HW_QMU_OFF + _offset))
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#define MGC_ReadQUCS16(base, _offset) \
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musb_readw(base, (USB_HW_QUCS_OFF + _offset))
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#define MGC_ReadQIRQ16(base, _offset) \
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musb_readw(base, (USB_HW_QIRQ_OFF + _offset))
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#define MGC_ReadQMU32(base, _offset) \
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musb_readl(base, (USB_HW_QMU_OFF + _offset))
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#define MGC_ReadQUCS32(base, _offset) \
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musb_readl(base, (USB_HW_QUCS_OFF + _offset))
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#define MGC_ReadQIRQ32(base, _offset) \
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musb_readl(base, (USB_HW_QIRQ_OFF + _offset))
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#define MGC_WriteQMU32(base, _offset, _data) \
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musb_writel(base, (USB_HW_QMU_OFF + _offset), _data)
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#define MGC_WriteQUCS32(base, _offset, _data) \
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musb_writel(base, (USB_HW_QUCS_OFF + _offset), _data)
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#define MGC_WriteQIRQ32(base, _offset, _data) \
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musb_writel(base, (USB_HW_QIRQ_OFF + _offset), _data)
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u8 PDU_calcCksum(u8 *data, int len);
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/* brief Define DMAQ GPD format */
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#define TGPD_FLAGS_HWO 0x01
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#define TGPD_IS_FLAGS_HWO(_pd) \
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(((struct TGPD *)_pd)->flag & TGPD_FLAGS_HWO)
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#define TGPD_SET_FLAGS_HWO(_pd) \
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(((struct TGPD *)_pd)->flag |= TGPD_FLAGS_HWO)
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#define TGPD_CLR_FLAGS_HWO(_pd) \
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(((struct TGPD *)_pd)->flag &= (~TGPD_FLAGS_HWO))
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#define TGPD_FORMAT_BDP 0x02
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#define TGPD_IS_FORMAT_BDP(_pd) \
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(((struct TGPD *)_pd)->flag & TGPD_FORMAT_BDP)
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#define TGPD_SET_FORMAT_BDP(_pd) \
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(((struct TGPD *)_pd)->flag |= TGPD_FORMAT_BDP)
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#define TGPD_CLR_FORMAT_BDP(_pd) \
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(((struct TGPD *)_pd)->flag &= (~TGPD_FORMAT_BDP))
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#define TGPD_SET_FLAG(_pd, _flag) \
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(((struct TGPD *)_pd)->flag = \
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(((struct TGPD *)_pd)->flag&(~TGPD_FLAGS_HWO))|(_flag))
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#define TGPD_GET_FLAG(_pd) \
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(((struct TGPD *)_pd)->flag & TGPD_FLAGS_HWO)
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#define TGPD_SET_CHKSUM(_pd, _n) \
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(((struct TGPD *)_pd)->chksum = PDU_calcCksum((u8 *)_pd, _n))
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#define TGPD_SET_CHKSUM_HWO(_pd, _n) \
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(((struct TGPD *)_pd)->chksum = PDU_calcCksum((u8 *)_pd, _n)-1)
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#define TGPD_GET_CHKSUM(_pd) (((struct TGPD *)_pd)->chksum)
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#define TGPD_SET_FORMAT(_pd, _fmt) \
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(((struct TGPD *)_pd)->flag =\
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(((struct TGPD *)_pd)->flag&(~TGPD_FORMAT_BDP))|(_fmt))
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#define TGPD_GET_FORMAT(_pd) \
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(((((struct TGPD *)_pd)->flag & TGPD_FORMAT_BDP)>>1))
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#ifdef CONFIG_MTK_MUSB_DRV_36BIT
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#define TGPD_SET_DataBUF_LEN(_pd, _len) \
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(((struct TGPD *)_pd)->gpd_w1.DataBufferLen = _len)
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#define TGPD_ADD_DataBUF_LEN(_pd, _len) \
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(((struct TGPD *)_pd)->gpd_w1.DataBufferLen += _len)
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#define TGPD_GET_DataBUF_LEN(_pd) \
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(((struct TGPD *)_pd)->gpd_w1.DataBufferLen)
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#else
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#define TGPD_SET_DataBUF_LEN(_pd, _len) \
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(((struct TGPD *)_pd)->DataBufferLen = _len)
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#define TGPD_ADD_DataBUF_LEN(_pd, _len) \
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(((struct TGPD *)_pd)->DataBufferLen += _len)
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#define TGPD_GET_DataBUF_LEN(_pd) (((struct TGPD *)_pd)->DataBufferLen)
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#endif
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#ifdef CONFIG_MTK_MUSB_DRV_36BIT
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#define TGPD_SET_NEXT(_pd, _next) \
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(((struct TGPD *)_pd)->pNext = (u32)_next)
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#define TGPD_SET_NEXT_TXHI(_pd, _next) \
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do { \
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((struct TGPD *) _pd)->gpd_w1.tx_haddr.hiaddr &= 0x0F; \
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((struct TGPD *) _pd)->gpd_w1.tx_haddr.hiaddr |=\
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((u8)_next << 4); \
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} while (0)
|
|
|
|
#define TGPD_SET_NEXT_RXHI(_pd, _next) \
|
|
do { \
|
|
((struct TGPD *) _pd)->gpd_b14.rx_haddr.hiaddr &= 0x0F; \
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|
((struct TGPD *) _pd)->gpd_b14.rx_haddr.hiaddr |=\
|
|
((u8)_next << 4); \
|
|
} while (0)
|
|
|
|
#define TGPD_GET_NEXT(_pd) \
|
|
((uintptr_t)((struct TGPD *)_pd)->pNext)
|
|
#define TGPD_GET_NEXT_TXHI(_pd) \
|
|
((uintptr_t)((struct TGPD *)_pd)->gpd_w1.tx_haddr.hiaddr >> 4)
|
|
#define TGPD_GET_NEXT_RXHI(_pd) \
|
|
((uintptr_t)((struct TGPD *)_pd)->gpd_b14.rx_haddr.hiaddr >> 4)
|
|
#define TGPD_GET_NEXT_TX(_pd) \
|
|
((struct TGPD *)(TGPD_GET_NEXT(_pd) | (TGPD_GET_NEXT_TXHI(_pd) << 32)))
|
|
#define TGPD_GET_NEXT_RX(_pd) \
|
|
((struct TGPD *)(TGPD_GET_NEXT(_pd) | (TGPD_GET_NEXT_RXHI(_pd) << 32)))
|
|
#define TGPD_SET_DATA(_pd, _data) \
|
|
(((struct TGPD *)_pd)->pBuf = (u32)_data)
|
|
#define TGPD_SET_DATA_TXHI(_pd, _next) \
|
|
do { \
|
|
((struct TGPD *)_pd)->gpd_w1.tx_haddr.hiaddr &= 0xF0; \
|
|
((struct TGPD *)_pd)->gpd_w1.tx_haddr.hiaddr |=\
|
|
((u8)_next & 0x0F); \
|
|
} while (0)
|
|
|
|
#define TGPD_SET_DATA_RXHI(_pd, _next) \
|
|
do { \
|
|
((struct TGPD *)_pd)->gpd_b14.rx_haddr.hiaddr &= 0xF0; \
|
|
((struct TGPD *)_pd)->gpd_b14.rx_haddr.hiaddr |=\
|
|
((u8)_next & 0x0F); \
|
|
} while (0)
|
|
|
|
#define TGPD_GET_DATA(_pd) ((uintptr_t)((struct TGPD *)_pd)->pBuf)
|
|
#define TGPD_GET_DATA_TXHI(_pd) \
|
|
((uintptr_t)((struct TGPD *)_pd)->gpd_w1.tx_haddr.hiaddr & 0x0F)
|
|
#define TGPD_GET_DATA_RXHI(_pd) \
|
|
((uintptr_t)((struct TGPD *)_pd)->gpd_b14.rx_haddr.hiaddr & 0x0F)
|
|
#define TGPD_GET_DATA_TX(_pd) \
|
|
((struct TGPD *)(TGPD_GET_DATA(_pd) | (TGPD_GET_DATA_TXHI(_pd) << 32)))
|
|
#define TGPD_GET_DATA_RX(_pd) \
|
|
((struct TGPD *)(TGPD_GET_DATA(_pd) | (TGPD_GET_DATA_RXHI(_pd) << 32)))
|
|
#else
|
|
#define TGPD_GET_NEXT_TX(_pd) TGPD_GET_NEXT(_pd)
|
|
#define TGPD_GET_NEXT_RX(_pd) TGPD_GET_NEXT(_pd)
|
|
|
|
#define TGPD_SET_NEXT(_pd, _next) \
|
|
(((struct TGPD *)_pd)->pNext = (u32)(uintptr_t)((struct TGPD *)_next))
|
|
#define TGPD_GET_NEXT(_pd) \
|
|
((struct TGPD *)(uintptr_t)((struct TGPD *)_pd)->pNext)
|
|
|
|
#define TGPD_GET_DATA_TX(_pd) TGPD_GET_DATA(_pd)
|
|
#define TGPD_GET_DATA_RX(_pd) TGPD_GET_DATA(_pd)
|
|
|
|
#define TGPD_SET_DATA(_pd, _data) \
|
|
(((struct TGPD *)_pd)->pBuf = (u32)(uintptr_t)_data)
|
|
#define TGPD_GET_DATA(_pd) \
|
|
((u8 *)(uintptr_t)((struct TGPD *)_pd)->pBuf)
|
|
#endif
|
|
|
|
#define TGPD_SET_BUF_LEN(_pd, _len) (((struct TGPD *)_pd)->bufLen = _len)
|
|
#define TGPD_ADD_BUF_LEN(_pd, _len) (((struct TGPD *)_pd)->bufLen += _len)
|
|
#define TGPD_GET_BUF_LEN(_pd) (((struct TGPD *)_pd)->bufLen)
|
|
|
|
#ifdef CONFIG_MTK_MUSB_DRV_36BIT
|
|
#define TGPD_SET_EXT_LEN(_pd, _len) \
|
|
(((struct TGPD *)_pd)->gpd_b14.ExtLength = _len)
|
|
#define TGPD_GET_EXT_LEN(_pd) \
|
|
(((struct TGPD *)_pd)->gpd_b14.ExtLength)
|
|
#else
|
|
#define TGPD_SET_EXT_LEN(_pd, _len) (((struct TGPD *)_pd)->ExtLength = _len)
|
|
#define TGPD_GET_EXT_LEN(_pd) (((struct TGPD *)_pd)->ExtLength)
|
|
#endif
|
|
|
|
#define TGPD_SET_EPaddr(_pd, _EP) (((struct TGPD *)_pd)->ZTepFlag = \
|
|
(((struct TGPD *)_pd)->ZTepFlag&0xF0)|(_EP))
|
|
#define TGPD_GET_EPaddr(_pd) (((struct TGPD *)_pd)->ZTepFlag & 0x0F)
|
|
|
|
#define TGPD_FORMAT_TGL 0x10
|
|
#define TGPD_IS_FORMAT_TGL(_pd) \
|
|
((((struct TGPD *)_pd)->ZTepFlag & TGPD_FORMAT_TGL))
|
|
#define TGPD_SET_FORMAT_TGL(_pd) \
|
|
((((struct TGPD *)_pd)->ZTepFlag |= TGPD_FORMAT_TGL))
|
|
#define TGPD_CLR_FORMAT_TGL(_pd) \
|
|
((((struct TGPD *)_pd)->ZTepFlag &= (~TGPD_FORMAT_TGL)))
|
|
#define TGPD_FORMAT_ZLP 0x20
|
|
#define TGPD_IS_FORMAT_ZLP(_pd) \
|
|
((((struct TGPD *)_pd)->ZTepFlag & TGPD_FORMAT_ZLP))
|
|
#define TGPD_SET_FORMAT_ZLP(_pd) \
|
|
((((struct TGPD *)_pd)->ZTepFlag |= TGPD_FORMAT_ZLP))
|
|
#define TGPD_CLR_FORMAT_ZLP(_pd) \
|
|
((((struct TGPD *)_pd)->ZTepFlag &= (~TGPD_FORMAT_ZLP)))
|
|
#define TGPD_SET_TGL(_pd, _TGL) \
|
|
(((struct TGPD *)_pd)->ZTepFlag |= ((_TGL) ? 0x10 : 0x00))
|
|
#define TGPD_GET_TGL(_pd) (((struct TGPD *)_pd)->ZTepFlag & 0x10 ? 1:0)
|
|
#define TGPD_SET_ZLP(_pd, _ZLP) \
|
|
(((struct TGPD *)_pd)->ZTepFlag |= ((_ZLP) ? 0x20 : 0x00))
|
|
#define TGPD_GET_ZLP(_pd) (((struct TGPD *)_pd)->ZTepFlag & 0x20 ? 1:0)
|
|
|
|
#define TGPD_FLAG_IOC 0x80
|
|
#define TGPD_SET_IOC(_pd) (((struct TGPD *)_pd)->flag |= TGPD_FLAG_IOC)
|
|
#define TGPD_CLR_IOC(_pd) (((struct TGPD *)_pd)->flag &= (~TGPD_FLAG_IOC))
|
|
|
|
extern void qmu_destroy_gpd_pool(struct device *dev);
|
|
extern int qmu_init_gpd_pool(struct device *dev);
|
|
extern void qmu_reset_gpd_pool(u32 ep_num, u8 isRx);
|
|
extern bool mtk_is_qmu_enabled(u8 EP_Num, u8 isRx);
|
|
extern void mtk_qmu_enable(struct musb *musb, u8 EP_Num, u8 isRx);
|
|
extern void mtk_qmu_insert_task(u8 EP_Num, u8 isRx,
|
|
dma_addr_t buf, u32 length, u8 zlp, u8 isioc);
|
|
extern void mtk_qmu_resume(u8 EP_Num, u8 isRx);
|
|
extern void qmu_done_rx(struct musb *musb, u8 ep_num);
|
|
extern void qmu_done_tx(struct musb *musb, u8 ep_num);
|
|
extern void mtk_disable_q(struct musb *musb, u8 ep_num, u8 isRx);
|
|
extern void mtk_qmu_irq_err(struct musb *musb, u32 qisar);
|
|
extern void flush_ep_csr(struct musb *musb, u8 ep_num, u8 isRx);
|
|
extern void mtk_qmu_stop(u8 ep_num, u8 isRx);
|
|
|
|
#define QMU_RX_SPLIT_BLOCK_SIZE (32*1024)
|
|
#define QMU_RX_SPLIT_THRE (64*1024)
|
|
extern u32 qmu_used_gpd_count(u8 isRx, u32 num);
|
|
extern u32 qmu_free_gpd_count(u8 isRx, u32 num);
|
|
extern void h_qmu_done_rx(struct musb *musb, u8 ep_num);
|
|
extern void h_qmu_done_tx(struct musb *musb, u8 ep_num);
|
|
#endif
|
|
#endif
|