6db4831e98
Android 14
658 lines
17 KiB
C
658 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*/
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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/* #include <asm/system.h> */
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#include "musb_core.h"
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#include "musbhsdma.h"
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#ifdef CONFIG_OF
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/* extern void __iomem *USB_BASE; */
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#endif
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#ifdef CONFIG_MTK_MUSB_DRV_36BIT
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#define USB_DMACNTL_ADDR36_EN (1 << 14)
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#define USB_DMACNT_COUNT_MASK (0xffffff)
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#define USB_DMACNT_HADDR_OFFSET (24)
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#define USB_DMACNT_HADDR_MASK (0xf)
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static u32 dma_extract_count(u32 count)
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{
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return (count & USB_DMACNT_COUNT_MASK);
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}
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static dma_addr_t dma_append_high_addr(
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dma_addr_t addr,
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void __iomem *mbase,
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u8 bchannel)
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{
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u64 hbit;
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hbit = musb_read_hsdma_count(mbase, bchannel);
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hbit = hbit >> USB_DMACNT_HADDR_OFFSET;
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addr = addr | (hbit << 32);
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return addr;
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}
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#endif
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static int dma_controller_start(struct dma_controller *c)
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{
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/* nothing to do */
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return 0;
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}
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static void dma_channel_release(struct dma_channel *channel);
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static int dma_controller_stop(struct dma_controller *c)
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{
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struct musb_dma_controller *controller = container_of(c,
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struct musb_dma_controller, controller);
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struct musb *musb = controller->private_data;
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struct dma_channel *channel;
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u8 bit;
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if (controller->used_channels != 0) {
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dev_notice(musb->controller, "Stopping DMA controller while channel active\n");
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for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
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if (controller->used_channels & (1 << bit)) {
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channel = &controller->channel[bit].channel;
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dma_channel_release(channel);
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if (!controller->used_channels)
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break;
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}
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}
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}
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return 0;
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}
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static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
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struct musb_hw_ep *hw_ep, u8 transmit)
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{
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struct musb_dma_controller *controller = container_of(c,
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struct musb_dma_controller, controller);
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struct musb *musb = controller->private_data;
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struct musb_dma_channel *musb_channel = NULL;
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struct dma_channel *channel = NULL;
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u8 bit;
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#ifdef CONFIG_MTK_MUSB_QMU_SUPPORT
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/* reserve dma channel 0 for QMU */
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for (bit = 1; bit < MUSB_HSDMA_CHANNELS; bit++) {
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#else
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for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
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#endif
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if (!(controller->used_channels & (1 << bit))) {
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controller->used_channels |= (1 << bit);
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musb_channel = &(controller->channel[bit]);
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musb_channel->controller = controller;
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musb_channel->idx = bit;
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if (musb->is_host) {
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musb_channel->epnum = hw_ep->epnum;
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} else {
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if (transmit) {
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/* dma irq will use
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* this member to get the hw ep.
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*/
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musb_channel->epnum =
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hw_ep->ep_in.current_epnum;
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} else
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/* after mapping,
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* hw ep num eques to the current num
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*/
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musb_channel->epnum =
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hw_ep->ep_out.current_epnum;
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}
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musb_channel->transmit = transmit;
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channel = &(musb_channel->channel);
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channel->private_data = musb_channel;
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channel->status = MUSB_DMA_STATUS_FREE;
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channel->max_len = 0x100000;
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/* Tx => mode 1; Rx => mode 0 */
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channel->desired_mode = transmit;
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channel->actual_len = 0;
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break;
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}
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}
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return channel;
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}
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static void dma_channel_release(struct dma_channel *channel)
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{
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struct musb_dma_channel *musb_channel = channel->private_data;
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u8 bchannel = musb_channel->idx;
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void __iomem *mbase = musb_channel->controller->base;
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musb_writew(mbase, MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
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MUSB_HSDMA_CONTROL), 0);
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channel->actual_len = 0;
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musb_channel->start_addr = 0;
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musb_channel->len = 0;
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musb_channel->controller->used_channels &= ~(1 << musb_channel->idx);
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channel->status = MUSB_DMA_STATUS_UNKNOWN;
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}
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static void configure_channel(struct dma_channel *channel,
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u16 packet_sz, u8 mode, dma_addr_t dma_addr, u32 len)
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{
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struct musb_dma_channel *musb_channel = channel->private_data;
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struct musb_dma_controller *controller = musb_channel->controller;
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void __iomem *mbase = controller->base;
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u8 bchannel = musb_channel->idx;
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u16 csr = 0;
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DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
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channel, packet_sz, (unsigned int)dma_addr, len, mode);
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if (mode) {
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csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
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if (len < packet_sz) {
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DBG(0, "%s:%d Error Here\n", __func__, __LINE__);
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return;
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}
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}
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csr |= MUSB_HSDMA_BURSTMODE_INCR16 << MUSB_HSDMA_BURSTMODE_SHIFT;
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csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
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| (1 << MUSB_HSDMA_ENABLE_SHIFT)
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| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
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| (musb_channel->transmit ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
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: 0);
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#ifdef CONFIG_MTK_MUSB_DRV_36BIT
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{
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u32 val;
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/* enable 36-bit support */
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csr |= USB_DMACNTL_ADDR36_EN;
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/* low address */
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musb_write_hsdma_addr(mbase, bchannel, dma_addr & 0xFFFFFFFF);
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/* count */
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val = len & USB_DMACNT_COUNT_MASK;
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/* high address */
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val |= (((dma_addr >> 32) & USB_DMACNT_HADDR_MASK)
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<< USB_DMACNT_HADDR_OFFSET);
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musb_write_hsdma_count(mbase, bchannel, val);
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}
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#else
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/* address/count */
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musb_write_hsdma_addr(mbase, bchannel, dma_addr);
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musb_write_hsdma_count(mbase, bchannel, len);
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#endif
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/* control (this should start things) */
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musb_writew(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), csr);
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DBG(5, "MUSB:DMA channel %d control reg is %x\n",
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bchannel, musb_readw(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL)));
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}
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static int dma_channel_program(struct dma_channel *channel,
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u16 packet_sz, u8 mode, dma_addr_t dma_addr, u32 len)
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{
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struct musb_dma_channel *musb_channel = channel->private_data;
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struct musb_dma_controller *controller = musb_channel->controller;
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struct musb *musb = controller->private_data;
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DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
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musb_channel->epnum,
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musb_channel->transmit ?
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"Tx" : "Rx", packet_sz, (unsigned int)dma_addr, len, mode);
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if (channel->status == MUSB_DMA_STATUS_UNKNOWN ||
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channel->status == MUSB_DMA_STATUS_BUSY) {
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DBG(0, "%s:%d Error Here\n", __func__, __LINE__);
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return -1;
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}
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/* Let targets check/tweak the arguments */
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if (musb->ops->adjust_channel_params) {
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int ret = musb->ops->adjust_channel_params(channel,
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packet_sz, &mode, &dma_addr, &len);
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if (ret)
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return ret;
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}
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#ifdef NEVER
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/*
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* The DMA engine in RTL1.8 and above cannot handle
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* DMA addresses that are not aligned to a 4 byte boundary.
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* It ends up masking the last two bits of the address
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* programmed in DMA_ADDR.
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*
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* Fail such DMA transfers, so that the backup PIO mode
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* can carry out the transfer
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*/
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if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
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return false;
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#endif
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channel->actual_len = 0;
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musb_channel->start_addr = dma_addr;
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musb_channel->len = len;
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musb_channel->max_packet_sz = packet_sz;
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channel->status = MUSB_DMA_STATUS_BUSY;
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configure_channel(channel, packet_sz, mode, dma_addr, len);
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return true;
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}
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static int dma_channel_abort(struct dma_channel *channel)
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{
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struct musb_dma_channel *musb_channel = channel->private_data;
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void __iomem *mbase = musb_channel->controller->base;
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u8 bchannel = musb_channel->idx;
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int offset;
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u16 csr;
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if (channel->status == MUSB_DMA_STATUS_BUSY) {
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if (musb_channel->transmit) {
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offset =
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MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR);
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/*
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* The programming guide says that we must clear
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* the DMAENAB bit before the DMAMODE bit...
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*/
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csr = musb_readw(mbase, offset);
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csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
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musb_writew(mbase, offset, csr);
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csr &= ~MUSB_TXCSR_DMAMODE;
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musb_writew(mbase, offset, csr);
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} else {
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offset = MUSB_EP_OFFSET
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(musb_channel->epnum, MUSB_RXCSR);
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csr = musb_readw(mbase, offset);
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csr &= ~(MUSB_RXCSR_AUTOCLEAR |
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MUSB_RXCSR_DMAENAB |
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MUSB_RXCSR_DMAMODE);
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musb_writew(mbase, offset, csr);
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}
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musb_writew(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
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MUSB_HSDMA_CONTROL), 0);
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musb_write_hsdma_addr(mbase, bchannel, 0);
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musb_write_hsdma_count(mbase, bchannel, 0);
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channel->status = MUSB_DMA_STATUS_FREE;
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}
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return 0;
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}
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static int dma_channel_pause(struct dma_channel *channel)
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{
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/*
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* Probably nothing to be done here. This is needed
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* only for certain DMA controllers which require
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* the DMA channel to be paused to get correct DMA
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* transfer residue
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*/
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return 0;
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}
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static int dma_channel_resume(struct dma_channel *channel)
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{
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/* Probably nothing to be done here */
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return 0;
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}
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static int dma_channel_tx_status(struct dma_channel *channel)
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{
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struct musb_dma_channel *musb_channel = channel->private_data;
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void __iomem *mbase = musb_channel->controller->base;
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u8 bchannel = musb_channel->idx;
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u32 count, residue;
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dma_addr_t addr;
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/*
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* Get the number of bytes left to be transferred over
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* DMA
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* The MUSB spec mentions "The DMA controller ADDR register
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* will have been incremented as packets were unloaded from
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* the fifo, the processor can determine the size of the
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* transfer by comparing the current value of ADDR against
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* the start address of the memory buffer
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*/
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/* residue = musb_read_hsdma_count(mbase, bchannel); */
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addr = musb_read_hsdma_addr(mbase, bchannel);
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#ifdef CONFIG_MTK_MUSB_DRV_36BIT
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addr = dma_append_high_addr(addr, mbase, bchannel);
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#endif
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count = addr - musb_channel->start_addr;
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residue = channel->prog_len - count;
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return residue;
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}
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static int dma_channel_check_residue(struct dma_channel *channel, u32 residue)
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{
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int status;
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/* In cases where we know the transfer length and were expecting
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* a DMA completion we could get into the DMA busy condition
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* here if the next packet is short and the EP interrupt occurs
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* before we receive dma_completion interrupt for current transfer
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* Wait for dma_completion. MUSB will interrupt us again for this
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* short packet when we clear the DMA bits
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*/
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if (!residue) {
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/* Wait for DMA completion */
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status = -EINPROGRESS;
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} else if (residue == channel->prog_len) {
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/* Nothing transferred over DMA? */
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/* WARN_ON(1); */
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status = -EINVAL;
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} else {
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/* residue looks OK */
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status = 0;
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}
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return status;
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}
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irqreturn_t dma_controller_irq(int irq, void *private_data)
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{
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struct musb_dma_controller *controller = private_data;
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struct musb *musb = controller->private_data;
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struct musb_dma_channel *musb_channel;
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struct dma_channel *channel;
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void __iomem *mbase = controller->base;
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irqreturn_t retval = IRQ_NONE;
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unsigned long flags;
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u8 bchannel;
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u8 int_hsdma;
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u32 count;
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u16 csr;
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dma_addr_t addr;
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spin_lock_irqsave(&musb->lock, flags);
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/* musb_read_clear_dma_interrupt */
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int_hsdma = musb_readb(musb->mregs, MUSB_HSDMA_INTR);
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/* make sure int_hsdma up to date before W1C */
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mb();
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musb_writeb(musb->mregs, MUSB_HSDMA_INTR, int_hsdma);
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/* musb_read_clear_dma_interrupt */
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if (!int_hsdma) {
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DBG(2, "spurious DMA irq\n");
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for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
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musb_channel = (struct musb_dma_channel *)
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&(controller->channel[bchannel]);
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channel = &musb_channel->channel;
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if (channel->status == MUSB_DMA_STATUS_BUSY) {
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count = musb_read_hsdma_count(mbase, bchannel);
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#ifdef CONFIG_MTK_MUSB_DRV_36BIT
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count = dma_extract_count(count);
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#endif
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if (count == 0)
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int_hsdma |= (1 << bchannel);
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}
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}
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DBG(2, "int_hsdma = 0x%x\n", int_hsdma);
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if (!int_hsdma)
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goto done;
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}
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for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
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if (int_hsdma & (1 << bchannel)) {
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musb_channel = (struct musb_dma_channel *)
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&(controller->channel[bchannel]);
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channel = &musb_channel->channel;
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DBG(1, "MUSB:DMA channel %d interrupt\n", bchannel);
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csr = musb_readw(mbase,
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MUSB_HSDMA_CHANNEL_OFFSET
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(bchannel, MUSB_HSDMA_CONTROL));
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if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
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musb_channel->channel.status
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= MUSB_DMA_STATUS_BUS_ABORT;
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} else {
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u8 devctl;
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addr = musb_read_hsdma_addr(mbase, bchannel);
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#ifdef CONFIG_MTK_MUSB_DRV_36BIT
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addr =
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dma_append_high_addr
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(addr, mbase, bchannel);
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#endif
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channel->actual_len = addr
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- musb_channel->start_addr;
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#ifdef NEVER
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channel->actual_len =
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musb_readl(mbase, USB_DMA_REALCOUNT(bchannel));
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#endif
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DBG(2,
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"[MUSB] channel %d ch %p, 0x%p -> 0x%p (%zu / %d) %s\n",
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bchannel,
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channel,
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(void *)(uintptr_t)
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musb_channel->start_addr,
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(void *)(uintptr_t)
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addr, channel->actual_len,
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musb_channel->len,
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(channel->actual_len
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< musb_channel->len)
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? "=> reconfig 0" : "=> complete");
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devctl = musb_readb(mbase, MUSB_DEVCTL);
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channel->status = MUSB_DMA_STATUS_FREE;
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/* completed */
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if ((devctl & MUSB_DEVCTL_HM)
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&& (musb_channel->transmit)
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&& ((channel->desired_mode == 0)
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|| (channel->actual_len &
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(musb_channel->max_packet_sz - 1)))
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) {
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u8 epnum = musb_channel->epnum;
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int offset = MUSB_EP_OFFSET(epnum,
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MUSB_TXCSR);
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u16 txcsr;
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host_tx_refcnt_inc(epnum);
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/*
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* The programming guide says that we
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* must clear DMAENAB before DMAMODE.
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*/
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musb_ep_select(mbase, epnum);
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txcsr = musb_readw(mbase, offset);
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txcsr &=
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~(MUSB_TXCSR_DMAENAB
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| MUSB_TXCSR_AUTOSET);
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musb_writew(mbase, offset, txcsr);
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/* Send out the packet */
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txcsr &= ~MUSB_TXCSR_DMAMODE;
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txcsr |= MUSB_TXCSR_TXPKTRDY;
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musb_writew(mbase, offset, txcsr);
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if (musb_host_db_workaround2
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&& musb->is_host)
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wait_tx_done(epnum, 2000000000);
|
|
} else
|
|
musb_dma_completion(musb,
|
|
musb_channel->epnum,
|
|
musb_channel->transmit);
|
|
}
|
|
}
|
|
}
|
|
DBG(4, "MUSB: DMA interrupt completino on ep\n");
|
|
|
|
retval = IRQ_HANDLED;
|
|
done:
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
|
return retval;
|
|
}
|
|
|
|
void dma_controller_destroy(struct dma_controller *c)
|
|
{
|
|
struct musb_dma_controller *controller = container_of(c,
|
|
struct musb_dma_controller, controller);
|
|
|
|
if (!controller)
|
|
return;
|
|
|
|
if (controller->irq)
|
|
free_irq(controller->irq, c);
|
|
|
|
kfree(controller);
|
|
}
|
|
|
|
struct dma_controller *dma_controller_create
|
|
(struct musb *musb, void __iomem *base)
|
|
{
|
|
struct musb_dma_controller *controller;
|
|
int irq = musb->dma_irq;
|
|
|
|
if ((irq <= 0) && (irq != SHARE_IRQ)) {
|
|
DBG(0, "[MUSB] No DMA interrupt line!\n");
|
|
return NULL;
|
|
}
|
|
|
|
controller = kzalloc(sizeof(*controller), GFP_KERNEL);
|
|
if (!controller)
|
|
return NULL;
|
|
|
|
controller->channel_count = MUSB_HSDMA_CHANNELS;
|
|
controller->private_data = musb;
|
|
controller->base = base;
|
|
|
|
controller->controller.start = dma_controller_start;
|
|
controller->controller.stop = dma_controller_stop;
|
|
controller->controller.channel_alloc = dma_channel_allocate;
|
|
controller->controller.channel_release = dma_channel_release;
|
|
controller->controller.channel_program = dma_channel_program;
|
|
controller->controller.channel_abort = dma_channel_abort;
|
|
controller->controller.channel_pause = dma_channel_pause;
|
|
controller->controller.channel_resume = dma_channel_resume;
|
|
controller->controller.tx_status = dma_channel_tx_status;
|
|
controller->controller.check_residue = dma_channel_check_residue;
|
|
|
|
if (irq != SHARE_IRQ) {
|
|
if (request_irq(irq, dma_controller_irq, 0,
|
|
dev_name(musb->controller), &controller->controller)) {
|
|
DBG(0, "request_irq %d failed!\n", irq);
|
|
dma_controller_destroy(&controller->controller);
|
|
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
controller->irq = irq;
|
|
|
|
return &controller->controller;
|
|
}
|
|
|
|
#define MUSB_HSDMA_REAL_COUNT 0x80
|
|
|
|
#define USB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
|
|
(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
|
|
|
|
#define usb_read_hsdma_addr(mbase, bchannel) \
|
|
musb_readl(mbase, \
|
|
USB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
|
|
|
|
#define usb_read_hsdma_ctrl(mbase, bchannel) \
|
|
musb_readb(mbase, \
|
|
MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL))
|
|
|
|
#define usb_read_hsdma_count(mbase, bchannel) \
|
|
musb_readl(mbase, \
|
|
MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
|
|
|
|
#define usb_read_hsdma_real_count(mbase, bchannel) \
|
|
musb_readl(mbase, \
|
|
MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_REAL_COUNT))
|
|
|
|
u8 USB_DMA_status(u8 *pbDMAen, u8 *pbDMAdir)
|
|
{
|
|
u8 bchannel;
|
|
u8 bDMAen = 0;
|
|
u8 bDMAdir = 0;
|
|
|
|
#ifdef CONFIG_OF
|
|
for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
|
|
bDMAen |=
|
|
(usb_read_hsdma_ctrl(mtk_musb->mregs, bchannel) & 0x01)
|
|
<< bchannel;
|
|
bDMAdir |=
|
|
((usb_read_hsdma_ctrl(mtk_musb->mregs, bchannel) & 0x02) >> 1)
|
|
<< bchannel;
|
|
}
|
|
#else
|
|
void __iomem *base = USB_BASE;
|
|
|
|
for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
|
|
bDMAen |= (usb_read_hsdma_ctrl(base, bchannel) & 0x01)
|
|
<< bchannel;
|
|
bDMAdir |= ((usb_read_hsdma_ctrl(base, bchannel) & 0x02) >> 1)
|
|
<< bchannel;
|
|
}
|
|
#endif
|
|
if (pbDMAen)
|
|
*pbDMAen = bDMAen;
|
|
if (pbDMAdir)
|
|
*pbDMAdir = bDMAdir;
|
|
if (bDMAen > 0)
|
|
return 1;
|
|
else
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(USB_DMA_status);
|
|
|
|
|
|
u32 USB_DMA_address(u32 *len, u8 bchannel)
|
|
{
|
|
#ifdef CONFIG_OF
|
|
/* void __iomem *base = USB_BASE; */
|
|
if (len) {
|
|
*len =
|
|
usb_read_hsdma_count(mtk_musb->mregs,
|
|
bchannel) + usb_read_hsdma_real_count
|
|
(mtk_musb->mregs, bchannel);
|
|
}
|
|
return (usb_read_hsdma_addr(mtk_musb->mregs, bchannel) -
|
|
usb_read_hsdma_real_count(mtk_musb->mregs, bchannel));
|
|
#else
|
|
void __iomem *base = (void *)USB_BASE;
|
|
|
|
if (len) {
|
|
*len =
|
|
usb_read_hsdma_count(base, bchannel) +
|
|
usb_read_hsdma_real_count(base, bchannel);
|
|
}
|
|
return usb_read_hsdma_addr(base, bchannel) -
|
|
usb_read_hsdma_real_count(base, bchannel);
|
|
#endif
|
|
}
|
|
EXPORT_SYMBOL(USB_DMA_address);
|