380 lines
12 KiB
C
380 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __VPU_DRV_H__
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#define __VPU_DRV_H__
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#include <linux/types.h>
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#define VPU_MAX_NUM_PORTS 32
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#define VPU_MAX_NUM_PROPS 32
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#define VPU_MAX_NUM_CORES 3
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extern unsigned int efuse_data;
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extern struct ion_client *my_ion_client;
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typedef uint8_t vpu_id_t;
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/* the last byte of string must be '/0' */
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//typedef char vpu_name_t[32];
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/**
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* Documentation index:
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* S1. Introduction
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* S2. Requirement
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* S3. Sample Use Cases
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*/
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/**
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* S1. Introduction
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* VPU driver is a transparent platform for data exchange with VPU firmware.
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* VPU firmware can dynamically load an algorithm and do image post-processing.
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*
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* VPU driver implements a model based on aspect of algorithm's requirements.
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* An algorithm needs the buffers of input and output, and execution arguments.
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* For all mentioned above, VPU driver defines 'Port' to describe the buffers
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* of input and output, and 'Info' to describe the specification of algorithm.
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* According the 'Port' and 'Info', a user could enque requests for doing
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* image post-processing. The diagram is as follows:
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*
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* +---------------+
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* | algo |
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* | ------ |
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* input port1-> | [info1] | ->output port1
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* | [info2] |
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* input port2-> | [info...] |
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* +---------------+
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*
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* With Algo's properties, a user can get enough information to do processing,
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* and assign the buffers to the matching ports. Moreover, a user algo can
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* specify execution arguments to a request.
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*
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* +------------------------+
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* | request |
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* | ------------- |
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* | [buffer1]=>input port1 |
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* | [buffer2]=>input port2 |
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* | [buffer3]=>input port3 |
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* | [setting1] |
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* | [setting2] |
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* | [setting...] |
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* +------------------------+
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*
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*/
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/**
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* S2. Requirement
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* 1. The processing order is FIFO. User should deque the request in order.
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* 2. The buffer address must be accessible by VPU. Use iommu to remap address
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* to the specific region.
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*
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*/
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/**
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* S3. Sample Use Cases
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* Provide 4 essential ioctl commands:
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* - VPU_IOCTL_GET_ALGO_INFO: get algo's port and info.
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*
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* struct vpu_algo algo;
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* strncpy(algo_n->name, "algo_name", sizeof(algo_n->name));
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* ioctl(fd, VPU_IOCTL_GET_ALGO_INFO, algo);
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*
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* - VPU_IOCTL_ENQUE_REQUEST: enque a request to user?<3F>s own queue.
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*
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* struct vpu_request req;
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* struct vpu_buffer *buf;
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* req->algo_id = algo->id;
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* req->buffer_count = 1;
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* buf = &req->buffers[0];
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* buf->format = VPU_BUF_FORMAT_IMG_Y8;
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* buf->width = 640;
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* buf->height = 360;
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* buf->plane_count = 1;
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* ioctl(fd, VPU_IOCTL_ENQ_REQUEST, req);
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*
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* - VPU_IOCTL_DEQUE_REQUEST: wait for request done, and get processing result.
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*
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* struct vpu_request req;
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* ioctl(fd, VPU_IOCTL_DEQUE_REQUEST, req);
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*
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* - VPU_IOCTL_FLUSH_REQUEST: flush all running request, and return failure if
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* not finished
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*
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* ioctl(fd, VPU_IOCTL_FLUSH_REQUEST, 0);
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*
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* - VPU_IOCTL_SET_POWER: request power mode and the performance.
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*
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* struct vpu_power power;
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* power.mode = VPU_POWER_MODE_DYNAMIC;
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* power.opp = VPU_POWER_OPP_UNREQUEST;
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* ioctl(fd, VPU_IOCTL_SET_POWER, power);
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*
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*/
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/*---------------------------------------------------------------------------*/
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/* VPU Property */
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/*---------------------------------------------------------------------------*/
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enum vpu_prop_type {
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VPU_PROP_TYPE_CHAR,
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VPU_PROP_TYPE_INT32,
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VPU_PROP_TYPE_INT64,
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VPU_PROP_TYPE_FLOAT,
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VPU_PROP_TYPE_DOUBLE,
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VPU_NUM_PROP_TYPES
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};
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enum vpu_prop_access {
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VPU_PROP_ACCESS_RDONLY,
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VPU_PROP_ACCESS_RDWR
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};
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/*
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* The description of properties contains the information about property values,
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* which are stored as compact memory. With the offset, it can get the specific
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* value from compact data.
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*
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* The example of struct vpu_prop_desc is as follows:
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* +--------+---------------------+--------+--------+-------+--------+
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* | id | name | offset | type | count | access |
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* +--------+---------------------+--------+--------+-------+--------+
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* | 0 | algo_version | 0 | int32 | 1 | RDONLY |
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* +--------+---------------------+--------+--------+-------+--------+
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* | 1 | field_1 | 4 | int32 | 2 | RDWR |
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* +--------+---------------------+--------+--------+-------+--------+
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* | 2 | field_2 | 12 | int64 | 1 | RDWR |
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* +--------+---------------------+--------+--------+-------+--------+
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*
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* Use a buffer to store all property data, which is a compact-format data.
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* The buffer's layout is described by prop_desc, using the offset could
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* get the specific data.
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*
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* The example of compact-format memory is as follows:
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* +--------+--------+--------+--------+--------+
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* | 0~3 | 4~7 | 8~11 | 12~15 | 16~23 |
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* +--------+--------+--------+--------+--------+
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* |alg_vers| field_1 | field_2 |
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* +--------+--------+--------+--------+--------+
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*
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*/
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struct vpu_prop_desc {
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vpu_id_t id;
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uint8_t type; /* the property's data type */
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uint8_t access; /* directional data exchange */
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uint32_t offset; /* offset = previous offset + previous size */
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uint32_t count; /* size = sizeof(type) x count */
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char name[32];
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};
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/*---------------------------------------------------------------------------*/
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/* VPU Ports */
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/*---------------------------------------------------------------------------*/
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enum vpu_port_usage {
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VPU_PORT_USAGE_IMAGE,
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VPU_PORT_USAGE_DATA,
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VPU_NUM_PORT_USAGES
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};
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enum vpu_port_dir {
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VPU_PORT_DIR_IN,
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VPU_PORT_DIR_OUT,
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VPU_PORT_DIR_IN_OUT,
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VPU_NUM_PORT_DIRS
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};
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/*
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* The ports contains the information about algorithm's input and output.
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* The each buffer on the vpu_request should be assigned a port id,
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* to let algorithm recognize every buffer's purpose.
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*
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* The example of vpu_port table is as follows:
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* +--------+---------------------+--------+--------+
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* | id | name | type | dir |
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* +--------+---------------------+--------+--------+
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* | 0 | image-in | IMAGE | IN |
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* +--------+---------------------+--------+--------+
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* | 1 | data-in | DATA | IN |
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* +--------+---------------------+--------+--------+
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* | 2 | image-out | IMAGE | OUT |
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* +--------+---------------------+--------+--------+
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* | 3 | image-temp | IMAGE | INOUT |
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* +--------+---------------------+--------+--------+
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*
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*/
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struct vpu_port {
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vpu_id_t id;
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uint8_t usage;
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uint8_t dir;
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char name[32];
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};
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/*---------------------------------------------------------------------------*/
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/* VPU Algo */
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/*---------------------------------------------------------------------------*/
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struct vpu_algo {
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vpu_id_t id[VPU_MAX_NUM_CORES];
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uint8_t port_count;
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uint8_t info_desc_count;
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uint8_t sett_desc_count;
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uint32_t info_length; /* the size of info data buffer */
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uint32_t sett_length;
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uint32_t bin_length;
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uint64_t info_ptr; /* the pointer to info data buffer */
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uint64_t bin_ptr; /* mva of algo bin, which is accessible by VPU */
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char name[32];
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struct vpu_prop_desc info_descs[VPU_MAX_NUM_PROPS];
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struct vpu_prop_desc sett_descs[VPU_MAX_NUM_PROPS];
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struct vpu_port ports[VPU_MAX_NUM_PORTS];
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};
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/*---------------------------------------------------------------------------*/
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/* VPU Register */
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/*---------------------------------------------------------------------------*/
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struct vpu_reg_value {
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uint32_t field;
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uint32_t value;
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};
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struct vpu_reg_values {
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uint8_t reg_count;
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struct vpu_reg_value *regs;
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};
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/*---------------------------------------------------------------------------*/
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/* VPU Power */
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/*---------------------------------------------------------------------------*/
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/*
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* Provide two power modes:
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* - dynamic: power-saving mode, it's on request to power on device.
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* - on: power on immediately
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*/
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enum vpu_power_mode {
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VPU_POWER_MODE_DYNAMIC,
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VPU_POWER_MODE_ON,
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};
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/*
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* Provide a set of OPPs(operation performance point)
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* The default opp is at the minimun performance,
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* and users could request the performance.
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*/
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enum vpu_power_opp {
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VPU_POWER_OPP_UNREQUEST = 0xFF,
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};
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struct vpu_power {
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uint8_t opp_step;
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uint8_t freq_step;
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uint32_t bw; /* unit: MByte/s */
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/* align with core index defined in user space header file */
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unsigned int core;
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};
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/*---------------------------------------------------------------------------*/
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/* VPU Plane */
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/*---------------------------------------------------------------------------*/
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struct vpu_plane {
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uint32_t stride; /* if buffer type is image */
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uint32_t length;
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uint64_t ptr; /* mva which is accessible by VPU */
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};
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enum vpu_buf_format {
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VPU_BUF_FORMAT_DATA,
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VPU_BUF_FORMAT_IMG_Y8,
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VPU_BUF_FORMAT_IMG_YV12,
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VPU_BUF_FORMAT_IMG_NV21,
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VPU_BUF_FORMAT_IMG_YUY2,
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VPU_BUF_FORMAT_IMPL_DEFINED = 0xFF,
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};
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struct vpu_buffer {
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vpu_id_t port_id;
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uint8_t format;
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uint8_t plane_count;
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uint32_t width;
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uint32_t height;
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struct vpu_plane planes[3];
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};
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enum vpu_req_status {
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VPU_REQ_STATUS_SUCCESS,
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VPU_REQ_STATUS_BUSY,
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VPU_REQ_STATUS_TIMEOUT,
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VPU_REQ_STATUS_INVALID,
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VPU_REQ_STATUS_FLUSH,
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VPU_REQ_STATUS_FAILURE,
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};
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struct vpu_request {
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/* to recognize the request is from which user */
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unsigned long *user_id;
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/* to recognize the request object id for unorder enque/deque
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* procedure
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*/
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uint64_t request_id;
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/* core index that user want to run the request on */
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unsigned int requested_core;
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/* the final occupied core index for request,
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* especially for request in common pool
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*/
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unsigned int occupied_core;
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vpu_id_t algo_id[VPU_MAX_NUM_CORES];
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int frame_magic; /* mapping for user space/kernel space */
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uint8_t status;
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uint8_t buffer_count;
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uint32_t sett_length;
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uint64_t sett_ptr; /* pointer to the request setting */
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uint64_t priv; /* reserved for user */
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struct vpu_buffer buffers[VPU_MAX_NUM_PORTS];
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/* driver usage only, fd in user space / ion handle in kernel */
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uint64_t buf_ion_infos[VPU_MAX_NUM_PORTS * 3];
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struct vpu_power power_param;
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};
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struct vpu_status {
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int vpu_core_index;
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bool vpu_core_available;
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int pool_list_size;
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};
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struct vpu_dev_debug_info {
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int dev_fd;
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char callername[32];
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pid_t open_pid;
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pid_t open_tgid;
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};
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#ifdef CONFIG_MTK_GZ_SUPPORT_SDSP
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extern int mtee_sdsp_enable(u32 on);
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#endif
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/*---------------------------------------------------------------------------*/
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/* IOCTL Command */
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/*---------------------------------------------------------------------------*/
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#define VPU_MAGICNO 'v'
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#define VPU_IOCTL_SET_POWER _IOW(VPU_MAGICNO, 0, int)
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#define VPU_IOCTL_ENQUE_REQUEST _IOW(VPU_MAGICNO, 1, int)
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#define VPU_IOCTL_DEQUE_REQUEST _IOWR(VPU_MAGICNO, 2, int)
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#define VPU_IOCTL_FLUSH_REQUEST _IOW(VPU_MAGICNO, 3, int)
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#define VPU_IOCTL_GET_ALGO_INFO _IOWR(VPU_MAGICNO, 4, int)
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#define VPU_IOCTL_LOCK _IOW(VPU_MAGICNO, 5, int)
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#define VPU_IOCTL_UNLOCK _IOW(VPU_MAGICNO, 6, int)
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#define VPU_IOCTL_LOAD_ALG_TO_POOL _IOW(VPU_MAGICNO, 7, int)
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#define VPU_IOCTL_REG_WRITE _IOW(VPU_MAGICNO, 8, int)
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#define VPU_IOCTL_REG_READ _IOWR(VPU_MAGICNO, 9, int)
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#define VPU_IOCTL_GET_CORE_STATUS _IOWR(VPU_MAGICNO, 10, int)
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#define VPU_IOCTL_OPEN_DEV_NOTICE _IOWR(VPU_MAGICNO, 11, int)
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#define VPU_IOCTL_CLOSE_DEV_NOTICE _IOWR(VPU_MAGICNO, 12, int)
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#define VPU_IOCTL_SDSP_SEC_LOCK _IOW(VPU_MAGICNO, 60, int)
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#define VPU_IOCTL_SDSP_SEC_UNLOCK _IOW(VPU_MAGICNO, 61, int)
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#endif
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