161 lines
4.2 KiB
C
161 lines
4.2 KiB
C
/*
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* Copyright © 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "brcmnand.h"
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struct iproc_nand_soc {
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struct brcmnand_soc soc;
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void __iomem *idm_base;
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void __iomem *ext_base;
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spinlock_t idm_lock;
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};
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#define IPROC_NAND_CTLR_READY_OFFSET 0x10
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#define IPROC_NAND_CTLR_READY BIT(0)
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#define IPROC_NAND_IO_CTRL_OFFSET 0x00
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#define IPROC_NAND_APB_LE_MODE BIT(24)
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#define IPROC_NAND_INT_CTRL_READ_ENABLE BIT(6)
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static bool iproc_nand_intc_ack(struct brcmnand_soc *soc)
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{
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struct iproc_nand_soc *priv =
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container_of(soc, struct iproc_nand_soc, soc);
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void __iomem *mmio = priv->ext_base + IPROC_NAND_CTLR_READY_OFFSET;
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u32 val = brcmnand_readl(mmio);
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if (val & IPROC_NAND_CTLR_READY) {
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brcmnand_writel(IPROC_NAND_CTLR_READY, mmio);
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return true;
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}
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return false;
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}
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static void iproc_nand_intc_set(struct brcmnand_soc *soc, bool en)
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{
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struct iproc_nand_soc *priv =
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container_of(soc, struct iproc_nand_soc, soc);
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void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET;
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u32 val;
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unsigned long flags;
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spin_lock_irqsave(&priv->idm_lock, flags);
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val = brcmnand_readl(mmio);
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if (en)
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val |= IPROC_NAND_INT_CTRL_READ_ENABLE;
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else
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val &= ~IPROC_NAND_INT_CTRL_READ_ENABLE;
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brcmnand_writel(val, mmio);
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spin_unlock_irqrestore(&priv->idm_lock, flags);
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}
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static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare,
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bool is_param)
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{
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struct iproc_nand_soc *priv =
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container_of(soc, struct iproc_nand_soc, soc);
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void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET;
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u32 val;
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unsigned long flags;
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spin_lock_irqsave(&priv->idm_lock, flags);
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val = brcmnand_readl(mmio);
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/*
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* In the case of BE or when dealing with NAND data, alway configure
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* the APB bus to LE mode before accessing the FIFO and back to BE mode
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* after the access is done
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*/
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if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) || !is_param) {
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if (prepare)
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val |= IPROC_NAND_APB_LE_MODE;
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else
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val &= ~IPROC_NAND_APB_LE_MODE;
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} else { /* when in LE accessing the parameter page, keep APB in BE */
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val &= ~IPROC_NAND_APB_LE_MODE;
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}
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brcmnand_writel(val, mmio);
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spin_unlock_irqrestore(&priv->idm_lock, flags);
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}
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static int iproc_nand_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct iproc_nand_soc *priv;
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struct brcmnand_soc *soc;
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struct resource *res;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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soc = &priv->soc;
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spin_lock_init(&priv->idm_lock);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iproc-idm");
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priv->idm_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->idm_base))
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return PTR_ERR(priv->idm_base);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iproc-ext");
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priv->ext_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->ext_base))
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return PTR_ERR(priv->ext_base);
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soc->ctlrdy_ack = iproc_nand_intc_ack;
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soc->ctlrdy_set_enabled = iproc_nand_intc_set;
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soc->prepare_data_bus = iproc_nand_apb_access;
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return brcmnand_probe(pdev, soc);
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}
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static const struct of_device_id iproc_nand_of_match[] = {
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{ .compatible = "brcm,nand-iproc" },
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{},
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};
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MODULE_DEVICE_TABLE(of, iproc_nand_of_match);
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static struct platform_driver iproc_nand_driver = {
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.probe = iproc_nand_probe,
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.remove = brcmnand_remove,
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.driver = {
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.name = "iproc_nand",
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.pm = &brcmnand_pm_ops,
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.of_match_table = iproc_nand_of_match,
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}
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};
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module_platform_driver(iproc_nand_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Brian Norris");
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MODULE_AUTHOR("Ray Jui");
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MODULE_DESCRIPTION("NAND driver for Broadcom IPROC-based SoCs");
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