103 lines
2.5 KiB
C
103 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Sean Wang <sean.wang@mediatek.com>
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*/
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include "mtk_eth_soc.h"
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int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
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{
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struct device_node *np;
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const char *str;
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int i, err;
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ss->ana_rgc3 = ana_rgc3;
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for (i = 0; i < MTK_MAX_DEVS; i++) {
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np = of_parse_phandle(r, "mediatek,sgmiisys", i);
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if (!np)
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break;
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ss->regmap[i] = syscon_node_to_regmap(np);
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if (IS_ERR(ss->regmap[i]))
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return PTR_ERR(ss->regmap[i]);
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err = of_property_read_string(np, "mediatek,physpeed", &str);
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if (err)
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return err;
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if (!strcmp(str, "2500"))
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ss->flags[i] |= MTK_SGMII_PHYSPEED_2500;
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else if (!strcmp(str, "1000"))
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ss->flags[i] |= MTK_SGMII_PHYSPEED_1000;
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else if (!strcmp(str, "auto"))
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ss->flags[i] |= MTK_SGMII_PHYSPEED_AN;
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else
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return -EINVAL;
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}
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return 0;
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}
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int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id)
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{
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unsigned int val;
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if (!ss->regmap[id])
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return -EINVAL;
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/* Setup the link timer and QPHY power up inside SGMIISYS */
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regmap_write(ss->regmap[id], SGMSYS_PCS_LINK_TIMER,
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SGMII_LINK_TIMER_DEFAULT);
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regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
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val |= SGMII_REMOTE_FAULT_DIS;
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regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
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regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
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val |= SGMII_AN_RESTART;
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regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
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regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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val &= ~SGMII_PHYA_PWD;
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regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
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return 0;
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}
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int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id)
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{
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unsigned int val;
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int mode;
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if (!ss->regmap[id])
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return -EINVAL;
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regmap_read(ss->regmap[id], ss->ana_rgc3, &val);
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val &= ~GENMASK(3, 2);
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mode = ss->flags[id] & MTK_SGMII_PHYSPEED_MASK;
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val |= (mode == MTK_SGMII_PHYSPEED_1000) ? 0 : BIT(2);
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regmap_write(ss->regmap[id], ss->ana_rgc3, val);
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/* disable SGMII AN */
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regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
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val &= ~BIT(12);
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regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
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/* SGMII force mode setting */
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val = 0x31120019;
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regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
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/* Release PHYA power down state */
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regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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val &= ~SGMII_PHYA_PWD;
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regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
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return 0;
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}
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