135 lines
3.4 KiB
C
135 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (c) 2021 MediaTek Inc.
|
|
*/
|
|
|
|
#ifndef __RT9750_LOAD_SWITCH_H
|
|
#define __RT9750_LOAD_SWITCH_H
|
|
|
|
#define RT9750_SLAVE_ADDR 0x67
|
|
#define RT9750_DEVICE_ID 0x00
|
|
#define RT9750_CHIP_REV_E1 0x00
|
|
|
|
enum rt9466_reg_addr {
|
|
RT9750_REG_CORE_CTRL0 = 0x00,
|
|
RT9750_REG_EVENT1_MASK,
|
|
RT9750_REG_EVENT2_MASK,
|
|
RT9750_REG_EVENT1,
|
|
RT9750_REG_EVENT2,
|
|
RT9750_REG_EVENT1_EN,
|
|
RT9750_REG_CONTROL,
|
|
RT9750_REG_ADC_CTRL,
|
|
RT9750_REG_SAMPLE_EN,
|
|
RT9750_REG_PROT_DLYOCP,
|
|
RT9750_REG_VBUS_OVP,
|
|
RT9750_REG_VOUT_REG,
|
|
RT9750_REG_VDROP_OVP,
|
|
RT9750_REG_VDROP_ALM,
|
|
RT9750_REG_VBAT_REG,
|
|
RT9750_REG_IBUS_OCP = 0x10,
|
|
RT9750_REG_TBUS_OTP,
|
|
RT9750_REG_TBAT_OTP,
|
|
RT9750_REG_VBUS_ADC2,
|
|
RT9750_REG_VBUS_ADC1,
|
|
RT9750_REG_IBUS_ADC2,
|
|
RT9750_REG_IBUS_ADC1,
|
|
RT9750_REG_VOUT_ADC2,
|
|
RT9750_REG_VOUT_ADC1,
|
|
RT9750_REG_VDROP_ADC2,
|
|
RT9750_REG_VDROP_ADC1,
|
|
RT9750_REG_VBAT_ADC2,
|
|
RT9750_REG_VBAT_ADC1,
|
|
RT9750_REG_TBUS_ADC2 = 0x1F,
|
|
RT9750_REG_TBUS_ADC1,
|
|
RT9750_REG_TBAT_ADC2,
|
|
RT9750_REG_TBAT_ADC1,
|
|
RT9750_REG_TDIE_ADC1,
|
|
RT9750_REG_EVENT_STATUS1,
|
|
RT9750_REG_EVENT_STATUS2,
|
|
RT9750_REG_EVENT_STATUS,
|
|
};
|
|
|
|
|
|
#define RT9750_VOUT_MAX 5000000
|
|
#define RT9750_VOUT_MIN 4200000
|
|
#define RT9750_VOUT_STEP 10000
|
|
#define RT9750_VOUT_NUM 81
|
|
|
|
#define RT9750_VBAT_MAX 5000000
|
|
#define RT9750_VBAT_MIN 4200000
|
|
#define RT9750_VBAT_STEP 10000
|
|
#define RT9750_VBAT_NUM 81
|
|
|
|
#define RT9750_IOCOCP_MAX 6500000
|
|
#define RT9750_IOCOCP_MIN 0
|
|
#define RT9750_IOCOCP_STEP 500000
|
|
#define RT9750_IOCOCP_NUM 14
|
|
|
|
#define RT9750_IBUSOC_MAX 6350000
|
|
#define RT9750_IBUSOC_MIN 0
|
|
#define RT9750_IBUSOC_STEP 50000
|
|
#define RT9750_IBUSOC_NUM 128
|
|
|
|
#define RT9750_VBUSOV_MAX 6500000
|
|
#define RT9750_VBUSOV_MIN 4200000
|
|
#define RT9750_VBUSOV_STEP 25000
|
|
#define RT9750_VBUSOV_NUM 93
|
|
|
|
|
|
/* ========== RT9750_REG_CONTROL 0x06 ============ */
|
|
#define RT9750_SHIFT_CHG_EN 4
|
|
#define RT9750_SHIFT_WDT 2
|
|
#define RT9750_MASK_CHG_EN (1 << RT9750_SHIFT_CHG_EN)
|
|
#define RT9750_MASK_WDT 0x0C
|
|
|
|
/* ========== RT9750_REG_PROT_DLYOCP 0x09 ============ */
|
|
#define RT9750_SHIFT_IOCOCP 4
|
|
#define RT9750_MASK_IOCOCP 0xF0
|
|
|
|
/* ========== RT9750_REG_VBUS_OVP 0x09 ============ */
|
|
#define RT9750_SHIFT_VBUSOVP 0
|
|
#define RT9750_MASK_VBUSOVP 0x7F
|
|
|
|
/* ========== RT9750_REG_VOUT_REG 0x0B ============ */
|
|
#define RT9750_SHIFT_VOUT 0
|
|
#define RT9750_MASK_VOUT 0x7F
|
|
|
|
/* ========== RT9750_REG_VBAT_REG 0x0E ============ */
|
|
#define RT9750_SHIFT_VBAT 0
|
|
#define RT9750_MASK_VBAT 0x7F
|
|
|
|
/* ========== RT9750_REG_IBUS_OC 0x10 ============ */
|
|
#define RT9750_SHIFT_IBUS_OCP 0
|
|
#define RT9750_MASK_IBUS_OCP 0x7F
|
|
|
|
/* ========== RT9750_REG_VBUS_ADC2 0x13 ============ */
|
|
#define RT9750_SHIFT_VBUS_ADC2 0
|
|
#define RT9750_MASK_VBUS_ADC2 0x1F
|
|
|
|
/* ========== RT9750_REG_IBUS_ADC2 0x15 ============ */
|
|
#define RT9750_SHIFT_IBUS_ADC2 0
|
|
#define RT9750_MASK_IBUS_ADC2 0x1F
|
|
|
|
/* ========== RT9750_REG_VOUT_ADC2 0x17 ============ */
|
|
#define RT9750_SHIFT_VOUT_ADC2 0
|
|
#define RT9750_MASK_VOUT_ADC2 0x1F
|
|
|
|
/* ========== RT9750_REG_VDROP_ADC2 0x19 ============ */
|
|
#define RT9750_SHIFT_VDROP_ADC2 0
|
|
#define RT9750_MASK_VDROP_ADC2 0x03
|
|
|
|
/* ========== RT9750_REG_VBAT_ADC2 0x1B ============ */
|
|
#define RT9750_SHIFT_VBAT_ADC2 0
|
|
#define RT9750_MASK_VBAT_ADC2 0x1F
|
|
|
|
/* ========== RT9750_REG_TBUS_ADC2 0x1F ============ */
|
|
#define RT9750_SHIFT_TBUS_ADC2 0
|
|
#define RT9750_MASK_TBUS_ADC2 0x0F
|
|
|
|
/* ========== RT9750_REG_TBAT_ADC2 0x21 ============ */
|
|
#define RT9750_SHIFT_TBAT_ADC2 0
|
|
|
|
#define RT9750_MASK_TBAT_ADC2 0x0F
|
|
|
|
#endif /* __RT9750_LOAD_SWITCH_H */
|