164 lines
3.8 KiB
C
164 lines
3.8 KiB
C
/*
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* linux/drivers/video/kyro/STG4000Ramdac.c
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*
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* Copyright (C) 2002 STMicroelectronics
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <video/kyro.h>
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#include "STG4000Reg.h"
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#include "STG4000Interface.h"
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static u32 STG_PIXEL_BUS_WIDTH = 128; /* 128 bit bus width */
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static u32 REF_CLOCK = 14318;
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int InitialiseRamdac(volatile STG4000REG __iomem * pSTGReg,
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u32 displayDepth,
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u32 displayWidth,
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u32 displayHeight,
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s32 HSyncPolarity,
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s32 VSyncPolarity, u32 * pixelClock)
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{
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u32 tmp = 0;
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u32 F = 0, R = 0, P = 0;
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u32 stride = 0;
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u32 ulPdiv = 0;
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u32 physicalPixelDepth = 0;
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/* Make sure DAC is in Reset */
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tmp = STG_READ_REG(SoftwareReset);
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if (tmp & 0x1) {
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CLEAR_BIT(1);
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STG_WRITE_REG(SoftwareReset, tmp);
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}
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/* Set Pixel Format */
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tmp = STG_READ_REG(DACPixelFormat);
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CLEAR_BITS_FRM_TO(0, 2);
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/* Set LUT not used from 16bpp to 32 bpp ??? */
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CLEAR_BITS_FRM_TO(8, 9);
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switch (displayDepth) {
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case 16:
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{
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physicalPixelDepth = 16;
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tmp |= _16BPP;
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break;
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}
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case 32:
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{
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/* Set for 32 bits per pixel */
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physicalPixelDepth = 32;
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tmp |= _32BPP;
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break;
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}
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default:
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return -EINVAL;
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}
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STG_WRITE_REG(DACPixelFormat, tmp);
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/* Workout Bus transfer bandwidth according to pixel format */
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ulPdiv = STG_PIXEL_BUS_WIDTH / physicalPixelDepth;
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/* Get Screen Stride in pixels */
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stride = displayWidth;
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/* Set Primary size info */
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tmp = STG_READ_REG(DACPrimSize);
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CLEAR_BITS_FRM_TO(0, 10);
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CLEAR_BITS_FRM_TO(12, 31);
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tmp |=
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((((displayHeight - 1) << 12) | (((displayWidth / ulPdiv) -
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1) << 23))
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| (stride / ulPdiv));
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STG_WRITE_REG(DACPrimSize, tmp);
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/* Set Pixel Clock */
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*pixelClock = ProgramClock(REF_CLOCK, *pixelClock, &F, &R, &P);
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/* Set DAC PLL Mode */
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tmp = STG_READ_REG(DACPLLMode);
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CLEAR_BITS_FRM_TO(0, 15);
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/* tmp |= ((P-1) | ((F-2) << 2) | ((R-2) << 11)); */
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tmp |= ((P) | ((F - 2) << 2) | ((R - 2) << 11));
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STG_WRITE_REG(DACPLLMode, tmp);
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/* Set Prim Address */
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tmp = STG_READ_REG(DACPrimAddress);
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CLEAR_BITS_FRM_TO(0, 20);
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CLEAR_BITS_FRM_TO(20, 31);
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STG_WRITE_REG(DACPrimAddress, tmp);
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/* Set Cursor details with HW Cursor disabled */
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tmp = STG_READ_REG(DACCursorCtrl);
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tmp &= ~SET_BIT(31);
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STG_WRITE_REG(DACCursorCtrl, tmp);
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tmp = STG_READ_REG(DACCursorAddr);
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CLEAR_BITS_FRM_TO(0, 20);
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STG_WRITE_REG(DACCursorAddr, tmp);
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/* Set Video Window */
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tmp = STG_READ_REG(DACVidWinStart);
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CLEAR_BITS_FRM_TO(0, 10);
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CLEAR_BITS_FRM_TO(16, 26);
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STG_WRITE_REG(DACVidWinStart, tmp);
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tmp = STG_READ_REG(DACVidWinEnd);
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CLEAR_BITS_FRM_TO(0, 10);
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CLEAR_BITS_FRM_TO(16, 26);
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STG_WRITE_REG(DACVidWinEnd, tmp);
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/* Set DAC Border Color to default */
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tmp = STG_READ_REG(DACBorderColor);
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CLEAR_BITS_FRM_TO(0, 23);
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STG_WRITE_REG(DACBorderColor, tmp);
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/* Set Graphics and Overlay Burst Control */
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STG_WRITE_REG(DACBurstCtrl, 0x0404);
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/* Set CRC Trigger to default */
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tmp = STG_READ_REG(DACCrcTrigger);
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CLEAR_BIT(0);
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STG_WRITE_REG(DACCrcTrigger, tmp);
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/* Set Video Port Control to default */
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tmp = STG_READ_REG(DigVidPortCtrl);
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CLEAR_BIT(8);
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CLEAR_BITS_FRM_TO(16, 27);
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CLEAR_BITS_FRM_TO(1, 3);
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CLEAR_BITS_FRM_TO(10, 11);
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STG_WRITE_REG(DigVidPortCtrl, tmp);
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return 0;
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}
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/* Ramdac control, turning output to the screen on and off */
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void DisableRamdacOutput(volatile STG4000REG __iomem * pSTGReg)
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{
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u32 tmp;
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/* Disable DAC for Graphics Stream Control */
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tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0);
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STG_WRITE_REG(DACStreamCtrl, tmp);
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}
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void EnableRamdacOutput(volatile STG4000REG __iomem * pSTGReg)
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{
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u32 tmp;
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/* Enable DAC for Graphics Stream Control */
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tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0);
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STG_WRITE_REG(DACStreamCtrl, tmp);
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}
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