314 lines
8.4 KiB
ArmAsm
314 lines
8.4 KiB
ArmAsm
/*
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* arch/arm/kernel/crunch-bits.S
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* Cirrus MaverickCrunch context switching and handling
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*
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* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
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*
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* Shamelessly stolen from the iWMMXt code by Nicolas Pitre, which is
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* Copyright (c) 2003-2004, MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/ptrace.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/assembler.h>
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#include <mach/ep93xx-regs.h>
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/*
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* We can't use hex constants here due to a bug in gas.
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*/
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#define CRUNCH_MVDX0 0
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#define CRUNCH_MVDX1 8
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#define CRUNCH_MVDX2 16
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#define CRUNCH_MVDX3 24
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#define CRUNCH_MVDX4 32
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#define CRUNCH_MVDX5 40
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#define CRUNCH_MVDX6 48
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#define CRUNCH_MVDX7 56
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#define CRUNCH_MVDX8 64
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#define CRUNCH_MVDX9 72
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#define CRUNCH_MVDX10 80
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#define CRUNCH_MVDX11 88
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#define CRUNCH_MVDX12 96
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#define CRUNCH_MVDX13 104
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#define CRUNCH_MVDX14 112
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#define CRUNCH_MVDX15 120
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#define CRUNCH_MVAX0L 128
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#define CRUNCH_MVAX0M 132
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#define CRUNCH_MVAX0H 136
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#define CRUNCH_MVAX1L 140
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#define CRUNCH_MVAX1M 144
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#define CRUNCH_MVAX1H 148
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#define CRUNCH_MVAX2L 152
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#define CRUNCH_MVAX2M 156
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#define CRUNCH_MVAX2H 160
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#define CRUNCH_MVAX3L 164
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#define CRUNCH_MVAX3M 168
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#define CRUNCH_MVAX3H 172
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#define CRUNCH_DSPSC 176
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#define CRUNCH_SIZE 184
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.text
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/*
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* Lazy switching of crunch coprocessor context
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*
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* r10 = struct thread_info pointer
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* r9 = ret_from_exception
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* lr = undefined instr exit
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*
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* called from prefetch exception handler with interrupts enabled
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*/
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ENTRY(crunch_task_enable)
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inc_preempt_count r10, r3
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ldr r8, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr
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ldr r1, [r8, #0x80]
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tst r1, #0x00800000 @ access to crunch enabled?
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bne 2f @ if so no business here
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mov r3, #0xaa @ unlock syscon swlock
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str r3, [r8, #0xc0]
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orr r1, r1, #0x00800000 @ enable access to crunch
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str r1, [r8, #0x80]
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ldr r3, =crunch_owner
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add r0, r10, #TI_CRUNCH_STATE @ get task crunch save area
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ldr r2, [sp, #60] @ current task pc value
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ldr r1, [r3] @ get current crunch owner
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str r0, [r3] @ this task now owns crunch
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sub r2, r2, #4 @ adjust pc back
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str r2, [sp, #60]
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ldr r2, [r8, #0x80]
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mov r2, r2 @ flush out enable (@@@)
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teq r1, #0 @ test for last ownership
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mov lr, r9 @ normal exit from exception
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beq crunch_load @ no owner, skip save
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crunch_save:
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cfstr64 mvdx0, [r1, #CRUNCH_MVDX0] @ save 64b registers
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cfstr64 mvdx1, [r1, #CRUNCH_MVDX1]
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cfstr64 mvdx2, [r1, #CRUNCH_MVDX2]
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cfstr64 mvdx3, [r1, #CRUNCH_MVDX3]
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cfstr64 mvdx4, [r1, #CRUNCH_MVDX4]
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cfstr64 mvdx5, [r1, #CRUNCH_MVDX5]
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cfstr64 mvdx6, [r1, #CRUNCH_MVDX6]
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cfstr64 mvdx7, [r1, #CRUNCH_MVDX7]
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cfstr64 mvdx8, [r1, #CRUNCH_MVDX8]
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cfstr64 mvdx9, [r1, #CRUNCH_MVDX9]
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cfstr64 mvdx10, [r1, #CRUNCH_MVDX10]
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cfstr64 mvdx11, [r1, #CRUNCH_MVDX11]
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cfstr64 mvdx12, [r1, #CRUNCH_MVDX12]
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cfstr64 mvdx13, [r1, #CRUNCH_MVDX13]
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cfstr64 mvdx14, [r1, #CRUNCH_MVDX14]
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cfstr64 mvdx15, [r1, #CRUNCH_MVDX15]
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#ifdef __ARMEB__
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#error fix me for ARMEB
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#endif
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cfmv32al mvfx0, mvax0 @ save 72b accumulators
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cfstr32 mvfx0, [r1, #CRUNCH_MVAX0L]
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cfmv32am mvfx0, mvax0
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cfstr32 mvfx0, [r1, #CRUNCH_MVAX0M]
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cfmv32ah mvfx0, mvax0
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cfstr32 mvfx0, [r1, #CRUNCH_MVAX0H]
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cfmv32al mvfx0, mvax1
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cfstr32 mvfx0, [r1, #CRUNCH_MVAX1L]
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cfmv32am mvfx0, mvax1
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cfstr32 mvfx0, [r1, #CRUNCH_MVAX1M]
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cfmv32ah mvfx0, mvax1
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cfstr32 mvfx0, [r1, #CRUNCH_MVAX1H]
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cfmv32al mvfx0, mvax2
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cfstr32 mvfx0, [r1, #CRUNCH_MVAX2L]
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cfmv32am mvfx0, mvax2
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cfstr32 mvfx0, [r1, #CRUNCH_MVAX2M]
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cfmv32ah mvfx0, mvax2
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cfstr32 mvfx0, [r1, #CRUNCH_MVAX2H]
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cfmv32al mvfx0, mvax3
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cfstr32 mvfx0, [r1, #CRUNCH_MVAX3L]
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cfmv32am mvfx0, mvax3
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cfstr32 mvfx0, [r1, #CRUNCH_MVAX3M]
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cfmv32ah mvfx0, mvax3
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cfstr32 mvfx0, [r1, #CRUNCH_MVAX3H]
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cfmv32sc mvdx0, dspsc @ save status word
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cfstr64 mvdx0, [r1, #CRUNCH_DSPSC]
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teq r0, #0 @ anything to load?
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cfldr64eq mvdx0, [r1, #CRUNCH_MVDX0] @ mvdx0 was clobbered
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beq 1f
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crunch_load:
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cfldr64 mvdx0, [r0, #CRUNCH_DSPSC] @ load status word
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cfmvsc32 dspsc, mvdx0
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cfldr32 mvfx0, [r0, #CRUNCH_MVAX0L] @ load 72b accumulators
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cfmval32 mvax0, mvfx0
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cfldr32 mvfx0, [r0, #CRUNCH_MVAX0M]
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cfmvam32 mvax0, mvfx0
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cfldr32 mvfx0, [r0, #CRUNCH_MVAX0H]
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cfmvah32 mvax0, mvfx0
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cfldr32 mvfx0, [r0, #CRUNCH_MVAX1L]
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cfmval32 mvax1, mvfx0
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cfldr32 mvfx0, [r0, #CRUNCH_MVAX1M]
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cfmvam32 mvax1, mvfx0
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cfldr32 mvfx0, [r0, #CRUNCH_MVAX1H]
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cfmvah32 mvax1, mvfx0
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cfldr32 mvfx0, [r0, #CRUNCH_MVAX2L]
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cfmval32 mvax2, mvfx0
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cfldr32 mvfx0, [r0, #CRUNCH_MVAX2M]
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cfmvam32 mvax2, mvfx0
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cfldr32 mvfx0, [r0, #CRUNCH_MVAX2H]
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cfmvah32 mvax2, mvfx0
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cfldr32 mvfx0, [r0, #CRUNCH_MVAX3L]
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cfmval32 mvax3, mvfx0
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cfldr32 mvfx0, [r0, #CRUNCH_MVAX3M]
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cfmvam32 mvax3, mvfx0
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cfldr32 mvfx0, [r0, #CRUNCH_MVAX3H]
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cfmvah32 mvax3, mvfx0
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cfldr64 mvdx0, [r0, #CRUNCH_MVDX0] @ load 64b registers
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cfldr64 mvdx1, [r0, #CRUNCH_MVDX1]
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cfldr64 mvdx2, [r0, #CRUNCH_MVDX2]
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cfldr64 mvdx3, [r0, #CRUNCH_MVDX3]
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cfldr64 mvdx4, [r0, #CRUNCH_MVDX4]
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cfldr64 mvdx5, [r0, #CRUNCH_MVDX5]
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cfldr64 mvdx6, [r0, #CRUNCH_MVDX6]
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cfldr64 mvdx7, [r0, #CRUNCH_MVDX7]
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cfldr64 mvdx8, [r0, #CRUNCH_MVDX8]
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cfldr64 mvdx9, [r0, #CRUNCH_MVDX9]
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cfldr64 mvdx10, [r0, #CRUNCH_MVDX10]
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cfldr64 mvdx11, [r0, #CRUNCH_MVDX11]
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cfldr64 mvdx12, [r0, #CRUNCH_MVDX12]
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cfldr64 mvdx13, [r0, #CRUNCH_MVDX13]
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cfldr64 mvdx14, [r0, #CRUNCH_MVDX14]
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cfldr64 mvdx15, [r0, #CRUNCH_MVDX15]
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1:
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#ifdef CONFIG_PREEMPT_COUNT
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get_thread_info r10
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#endif
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2: dec_preempt_count r10, r3
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ret lr
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/*
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* Back up crunch regs to save area and disable access to them
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* (mainly for gdb or sleep mode usage)
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*
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* r0 = struct thread_info pointer of target task or NULL for any
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*/
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ENTRY(crunch_task_disable)
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stmfd sp!, {r4, r5, lr}
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mrs ip, cpsr
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orr r2, ip, #PSR_I_BIT @ disable interrupts
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msr cpsr_c, r2
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ldr r4, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr
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ldr r3, =crunch_owner
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add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area
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ldr r1, [r3] @ get current crunch owner
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teq r1, #0 @ any current owner?
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beq 1f @ no: quit
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teq r0, #0 @ any owner?
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teqne r1, r2 @ or specified one?
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bne 1f @ no: quit
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ldr r5, [r4, #0x80] @ enable access to crunch
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mov r2, #0xaa
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str r2, [r4, #0xc0]
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orr r5, r5, #0x00800000
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str r5, [r4, #0x80]
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mov r0, #0 @ nothing to load
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str r0, [r3] @ no more current owner
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ldr r2, [r4, #0x80] @ flush out enable (@@@)
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mov r2, r2
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bl crunch_save
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mov r2, #0xaa @ disable access to crunch
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str r2, [r4, #0xc0]
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bic r5, r5, #0x00800000
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str r5, [r4, #0x80]
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ldr r5, [r4, #0x80] @ flush out enable (@@@)
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mov r5, r5
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1: msr cpsr_c, ip @ restore interrupt mode
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ldmfd sp!, {r4, r5, pc}
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/*
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* Copy crunch state to given memory address
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*
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* r0 = struct thread_info pointer of target task
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* r1 = memory address where to store crunch state
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*
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* this is called mainly in the creation of signal stack frames
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*/
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ENTRY(crunch_task_copy)
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mrs ip, cpsr
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orr r2, ip, #PSR_I_BIT @ disable interrupts
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msr cpsr_c, r2
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ldr r3, =crunch_owner
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add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area
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ldr r3, [r3] @ get current crunch owner
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teq r2, r3 @ does this task own it...
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beq 1f
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@ current crunch values are in the task save area
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msr cpsr_c, ip @ restore interrupt mode
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mov r0, r1
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mov r1, r2
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mov r2, #CRUNCH_SIZE
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b memcpy
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1: @ this task owns crunch regs -- grab a copy from there
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mov r0, #0 @ nothing to load
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mov r3, lr @ preserve return address
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bl crunch_save
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msr cpsr_c, ip @ restore interrupt mode
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ret r3
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/*
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* Restore crunch state from given memory address
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*
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* r0 = struct thread_info pointer of target task
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* r1 = memory address where to get crunch state from
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*
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* this is used to restore crunch state when unwinding a signal stack frame
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*/
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ENTRY(crunch_task_restore)
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mrs ip, cpsr
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orr r2, ip, #PSR_I_BIT @ disable interrupts
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msr cpsr_c, r2
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ldr r3, =crunch_owner
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add r2, r0, #TI_CRUNCH_STATE @ get task crunch save area
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ldr r3, [r3] @ get current crunch owner
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teq r2, r3 @ does this task own it...
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beq 1f
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@ this task doesn't own crunch regs -- use its save area
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msr cpsr_c, ip @ restore interrupt mode
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mov r0, r2
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mov r2, #CRUNCH_SIZE
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b memcpy
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1: @ this task owns crunch regs -- load them directly
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mov r0, r1
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mov r1, #0 @ nothing to save
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mov r3, lr @ preserve return address
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bl crunch_load
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msr cpsr_c, ip @ restore interrupt mode
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ret r3
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