323 lines
13 KiB
Plaintext
Executable file
323 lines
13 KiB
Plaintext
Executable file
What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Enable/disable tracing on this specific trace entiry.
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Enabling a source implies the source has been configured
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properly and a sink has been identidifed for it. The path
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of coresight components linking the source to the sink is
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configured and managed automatically by the coresight framework.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: Select which address comparator or pair (of comparators) to
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work with.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used in conjunction with @addr_idx. Specifies
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characteristics about the address comparator being configure,
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for example the access type, the kind of instruction to trace,
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processor contect ID to trigger on, etc. Individual fields in
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the access type register may vary on the version of the trace
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entity.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used in conjunction with @addr_idx. Specifies the range of
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addresses to trigger on. Inclusion or exclusion is specificed
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in the corresponding access type register.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used in conjunction with @addr_idx. Specifies the single
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address to trigger on, highly influenced by the configuration
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options of the corresponding access type register.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used in conjunction with @addr_idx. Specifies the single
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address to start tracing on, highly influenced by the
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configuration options of the corresponding access type register.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used in conjunction with @addr_idx. Specifies the single
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address to stop tracing on, highly influenced by the
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configuration options of the corresponding access type register.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Specifies the counter to work on.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_event
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used in conjunction with cntr_idx, give access to the
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counter event register.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_val
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used in conjunction with cntr_idx, give access to the
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counter value register.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_val
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used in conjunction with cntr_idx, give access to the
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counter reload value register.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_rld_event
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used in conjunction with cntr_idx, give access to the
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counter reload event register.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_idx
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Specifies the index of the context ID register to be
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selected.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_mask
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Mask to apply to all the context ID comparator.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/ctxid_pid
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Used with the ctxid_idx, specify with context ID to trigger
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on.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_event
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Defines which event triggers a trace.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/etmsr
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Gives access to the ETM status register, which holds
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programming information and status on certains events.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/fifofull_level
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Number of byte left in the fifo before considering it full.
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Depending on the tracer's version, can also hold threshold for
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data suppression.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mode
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Interface with the driver's 'mode' field, controlling
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various aspect of the trace entity such as time stamping,
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context ID size and cycle accurate tracing. Driver specific
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and bound to change depending on the driver.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_addr_cmp
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Provides the number of address comparators pairs accessible
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on a trace unit, as specified by bit 3:0 of register ETMCCR.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_cntr
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Provides the number of counters accessible on a trace unit,
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as specified by bit 15:13 of register ETMCCR.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/nr_ctxid_cmp
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Provides the number of context ID comparator available on a
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trace unit, as specified by bit 25:24 of register ETMCCR.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/reset
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (W) Cancels all configuration on a trace unit and set it back
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to its boot configuration.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_12_event
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Defines the event that causes the sequencer to transition
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from state 1 to state 2.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_13_event
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Defines the event that causes the sequencer to transition
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from state 1 to state 3.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_21_event
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Defines the event that causes the sequencer to transition
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from state 2 to state 1.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_23_event
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Defines the event that causes the sequencer to transition
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from state 2 to state 3.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_31_event
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Defines the event that causes the sequencer to transition
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from state 3 to state 1.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/seq_32_event
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Defines the event that causes the sequencer to transition
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from state 3 to state 2.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/curr_seq_state
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Holds the current state of the sequencer.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/sync_freq
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Holds the trace synchronization frequency value - must be
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programmed with the various implementation behavior in mind.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/timestamp_event
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Defines an event that requests the insertion of a timestamp
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into the trace stream.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/traceid
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Holds the trace ID that will appear in the trace stream
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coming from this trace entity.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/trigger_event
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Define the event that controls the trigger.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cpu
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Date: October 2015
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KernelVersion: 4.4
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RO) Holds the cpu number this tracer is affined to.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccr
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Date: September 2015
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KernelVersion: 4.4
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RO) Print the content of the ETM Configuration Code register
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(0x004). The value is read directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccer
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Date: September 2015
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KernelVersion: 4.4
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RO) Print the content of the ETM Configuration Code Extension
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register (0x1e8). The value is read directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmscr
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Date: September 2015
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KernelVersion: 4.4
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RO) Print the content of the ETM System Configuration
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register (0x014). The value is read directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmidr
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Date: September 2015
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KernelVersion: 4.4
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RO) Print the content of the ETM ID register (0x1e4). The
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value is read directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmcr
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Date: September 2015
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KernelVersion: 4.4
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RO) Print the content of the ETM Main Control register (0x000).
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The value is read directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtraceidr
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Date: September 2015
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KernelVersion: 4.4
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RO) Print the content of the ETM Trace ID register (0x200).
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The value is read directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmteevr
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Date: September 2015
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KernelVersion: 4.4
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RO) Print the content of the ETM Trace Enable Event register
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(0x020). The value is read directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtsscr
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Date: September 2015
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KernelVersion: 4.4
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RO) Print the content of the ETM Trace Start/Stop Conrol
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register (0x018). The value is read directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr1
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Date: September 2015
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KernelVersion: 4.4
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RO) Print the content of the ETM Enable Conrol #1
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register (0x024). The value is read directly from the HW.
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What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmtecr2
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Date: September 2015
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KernelVersion: 4.4
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RO) Print the content of the ETM Enable Conrol #2
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register (0x01c). The value is read directly from the HW.
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