157 lines
6 KiB
Plaintext
Executable file
157 lines
6 KiB
Plaintext
Executable file
The following describes the current state of the NetWinder's floating point
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emulator.
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In the following nomenclature is used to describe the floating point
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instructions. It follows the conventions in the ARM manual.
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<S|D|E> = <single|double|extended>, no default
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{P|M|Z} = {round to +infinity,round to -infinity,round to zero},
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default = round to nearest
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Note: items enclosed in {} are optional.
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Floating Point Coprocessor Data Transfer Instructions (CPDT)
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------------------------------------------------------------
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LDF/STF - load and store floating
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<LDF|STF>{cond}<S|D|E> Fd, Rn
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<LDF|STF>{cond}<S|D|E> Fd, [Rn, #<expression>]{!}
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<LDF|STF>{cond}<S|D|E> Fd, [Rn], #<expression>
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These instructions are fully implemented.
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LFM/SFM - load and store multiple floating
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Form 1 syntax:
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<LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn]
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<LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn, #<expression>]{!}
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<LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn], #<expression>
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Form 2 syntax:
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<LFM|SFM>{cond}<FD,EA> Fd, <count>, [Rn]{!}
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These instructions are fully implemented. They store/load three words
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for each floating point register into the memory location given in the
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instruction. The format in memory is unlikely to be compatible with
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other implementations, in particular the actual hardware. Specific
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mention of this is made in the ARM manuals.
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Floating Point Coprocessor Register Transfer Instructions (CPRT)
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----------------------------------------------------------------
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Conversions, read/write status/control register instructions
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FLT{cond}<S,D,E>{P,M,Z} Fn, Rd Convert integer to floating point
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FIX{cond}{P,M,Z} Rd, Fn Convert floating point to integer
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WFS{cond} Rd Write floating point status register
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RFS{cond} Rd Read floating point status register
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WFC{cond} Rd Write floating point control register
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RFC{cond} Rd Read floating point control register
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FLT/FIX are fully implemented.
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RFS/WFS are fully implemented.
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RFC/WFC are fully implemented. RFC/WFC are supervisor only instructions, and
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presently check the CPU mode, and do an invalid instruction trap if not called
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from supervisor mode.
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Compare instructions
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CMF{cond} Fn, Fm Compare floating
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CMFE{cond} Fn, Fm Compare floating with exception
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CNF{cond} Fn, Fm Compare negated floating
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CNFE{cond} Fn, Fm Compare negated floating with exception
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These are fully implemented.
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Floating Point Coprocessor Data Instructions (CPDT)
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---------------------------------------------------
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Dyadic operations:
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ADF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - add
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SUF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - subtract
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RSF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse subtract
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MUF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - multiply
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DVF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - divide
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RDV{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse divide
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These are fully implemented.
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FML{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast multiply
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FDV{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast divide
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FRD{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast reverse divide
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These are fully implemented as well. They use the same algorithm as the
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non-fast versions. Hence, in this implementation their performance is
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equivalent to the MUF/DVF/RDV instructions. This is acceptable according
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to the ARM manual. The manual notes these are defined only for single
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operands, on the actual FPA11 hardware they do not work for double or
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extended precision operands. The emulator currently does not check
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the requested permissions conditions, and performs the requested operation.
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RMF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - IEEE remainder
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This is fully implemented.
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Monadic operations:
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MVF{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - move
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MNF{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - move negated
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These are fully implemented.
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ABS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - absolute value
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SQT{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - square root
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RND{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - round
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These are fully implemented.
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URD{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - unnormalized round
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NRM{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - normalize
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These are implemented. URD is implemented using the same code as the RND
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instruction. Since URD cannot return a unnormalized number, NRM becomes
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a NOP.
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Library calls:
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POW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - power
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RPW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse power
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POL{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - polar angle (arctan2)
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LOG{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base 10
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LGN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base e
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EXP{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - exponent
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SIN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - sine
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COS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - cosine
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TAN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - tangent
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ASN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arcsine
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ACS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arccosine
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ATN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arctangent
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These are not implemented. They are not currently issued by the compiler,
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and are handled by routines in libc. These are not implemented by the FPA11
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hardware, but are handled by the floating point support code. They should
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be implemented in future versions.
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Signalling:
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Signals are implemented. However current ELF kernels produced by Rebel.com
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have a bug in them that prevents the module from generating a SIGFPE. This
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is caused by a failure to alias fp_current to the kernel variable
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current_set[0] correctly.
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The kernel provided with this distribution (vmlinux-nwfpe-0.93) contains
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a fix for this problem and also incorporates the current version of the
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emulator directly. It is possible to run with no floating point module
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loaded with this kernel. It is provided as a demonstration of the
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technology and for those who want to do floating point work that depends
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on signals. It is not strictly necessary to use the module.
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A module (either the one provided by Russell King, or the one in this
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distribution) can be loaded to replace the functionality of the emulator
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built into the kernel.
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