139 lines
6.2 KiB
Plaintext
Executable file
139 lines
6.2 KiB
Plaintext
Executable file
Qualcomm External Bus Interface 2 (EBI2)
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The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
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external memory (such as NAND or other memory-mapped peripherals) whereas
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LCDC handles LCD displays.
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As it says it connects devices to an external bus interface, meaning address
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lines (up to 9 address lines so can only address 1KiB external memory space),
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data lines (16 bits), OE (output enable), ADV (address valid, used on some
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NOR flash memories), WE (write enable). This on top of 6 different chip selects
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(CS0 thru CS5) so that in theory 6 different devices can be connected.
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Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
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and the bus can only come out on these pins, however if some of the pins are
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unused they can be left unconnected or remuxed to be used as GPIO or in some
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cases other orthogonal functions as well.
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Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
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The chip selects have the following memory range assignments. This region of
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memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
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Chip Select Physical address base
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CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
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CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
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CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
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CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
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CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
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CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
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The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
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August 6, 2012 contains some incomplete documentation of the EBI2.
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FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
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We have not been able to figure out which bit fields these correspond to
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in the hardware, or what valid values exist. The current hypothesis is that
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this is something just used on the FAST chip selects and that the SLOW
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chip selects are understood fully. There is also a "byte device enable"
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flag somewhere for 8bit memories.
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FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
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unclear what this means, if they are mutually exclusive or can be used
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together, or if some chip selects are hardwired to be FAST and others are SLOW
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by design.
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The XMEM registers are totally undocumented but could be partially decoded
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because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
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similar register layout, see: http://www.cypress.com/file/105771/download
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Required properties:
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- compatible: should be one of:
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"qcom,msm8660-ebi2"
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"qcom,apq8060-ebi2"
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- #address-cells: should be <2>: the first cell is the chipselect,
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the second cell is the offset inside the memory range
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- #size-cells: should be <1>
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- ranges: should be set to:
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ranges = <0 0x0 0x1a800000 0x00800000>,
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<1 0x0 0x1b000000 0x00800000>,
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<2 0x0 0x1b800000 0x00800000>,
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<3 0x0 0x1d000000 0x08000000>,
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<4 0x0 0x1c800000 0x00800000>,
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<5 0x0 0x1c000000 0x00800000>;
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- reg: two ranges of registers: EBI2 config and XMEM config areas
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- reg-names: should be "ebi2", "xmem"
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- clocks: two clocks, EBI_2X and EBI
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- clock-names: should be "ebi2x", "ebi2"
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Optional subnodes:
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- Nodes inside the EBI2 will be considered device nodes.
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The following optional properties are properties that can be tagged onto
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any device subnode. We are assuming that there can be only ONE device per
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chipselect subnode, else the properties will become ambigous.
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Optional properties arrays for SLOW chip selects:
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- qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
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drive the data bus after OE is de-asserted, in order to avoid contention on
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the data bus. They are inserted when reading one CS and switching to another
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CS or read followed by write on the same CS. Valid values 0 thru 15. Minimum
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value is actually 1, so a value of 0 will still yield 1 recovery cycle.
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- qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
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inserted after every write minimum 1. The data out is driven from the time
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WE is asserted until CS is asserted. With a hold of 1 (value = 0), the CS
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stays active for 1 extra cycle etc. Valid values 0 thru 15.
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- qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
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the first write to a page or burst memory. Valid values 0 thru 255.
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- qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
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first read to a page or burst memory. Valid values 0 thru 255.
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- qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
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cycle. Valid values 0 thru 15.
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- qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
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cycle. Valid values 0 thru 15.
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Optional properties arrays for FAST chip selects:
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- qcom,xmem-address-hold-enable: this is a boolean property stating that we
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shall hold the address for an extra cycle to meet hold time requirements
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with ADV assertion.
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- qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
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assertion, with respect to the cycle where ADV (address valid) is asserted.
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2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
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- qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
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read transfer. For a single read transfer this will be the time from CS
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assertion to OE assertion. Valid values 0 thru 15.
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Example:
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ebi2@1a100000 {
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compatible = "qcom,apq8060-ebi2";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0x0 0x1a800000 0x00800000>,
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<1 0x0 0x1b000000 0x00800000>,
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<2 0x0 0x1b800000 0x00800000>,
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<3 0x0 0x1d000000 0x08000000>,
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<4 0x0 0x1c800000 0x00800000>,
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<5 0x0 0x1c000000 0x00800000>;
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reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
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reg-names = "ebi2", "xmem";
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clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
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clock-names = "ebi2x", "ebi2";
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/* Make sure to set up the pin control for the EBI2 */
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pinctrl-names = "default";
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pinctrl-0 = <&foo_ebi2_pins>;
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foo-ebi2@2,0 {
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compatible = "foo";
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reg = <2 0x0 0x100>;
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(...)
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qcom,xmem-recovery-cycles = <0>;
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qcom,xmem-write-hold-cycles = <3>;
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qcom,xmem-write-delta-cycles = <31>;
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qcom,xmem-read-delta-cycles = <28>;
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qcom,xmem-write-wait-cycles = <9>;
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qcom,xmem-read-wait-cycles = <9>;
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};
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};
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