108 lines
3.1 KiB
Plaintext
Executable file
108 lines
3.1 KiB
Plaintext
Executable file
NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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for muxing and gating Tegra's clocks, and setting their rates.
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Required properties :
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- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
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- reg : Should contain CAR registers location and length
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- clocks : Should contain phandle and clock specifiers for two clocks:
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the 32 KHz "32k_in", and the board-specific oscillator "osc".
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- #clock-cells : Should be 1.
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In clock consumers, this cell represents the clock ID exposed by the
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CAR. The assignments may be found in the header files
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<dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
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to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
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(for Tegra124-specific clocks).
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- #reset-cells : Should be 1.
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In clock consumers, this cell represents the bit number in the CAR's
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array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
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- nvidia,external-memory-controller : phandle of the EMC driver.
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The node should contain a "emc-timings" subnode for each supported RAM type (see
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field RAM_CODE in register PMC_STRAPPING_OPT_A).
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Required properties for "emc-timings" nodes :
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- nvidia,ram-code : Should contain the value of RAM_CODE this timing set
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is used for.
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Each "emc-timings" node should contain a "timing" subnode for every supported
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EMC clock rate.
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Required properties for "timing" nodes :
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- clock-frequency : Should contain the memory clock rate to which this timing
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relates.
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- nvidia,parent-clock-frequency : Should contain the rate at which the current
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parent of the EMC clock should be running at this timing.
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names : Must include the following entries:
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- emc-parent : the clock that should be the parent of the EMC clock at this
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timing.
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Example SoC include file:
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/ {
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tegra_car: clock@60006000 {
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compatible = "nvidia,tegra124-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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nvidia,external-memory-controller = <&emc>;
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};
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usb@c5004000 {
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clocks = <&tegra_car TEGRA124_CLK_USB2>;
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};
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};
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Example board file:
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/ {
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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osc: clock@0 {
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compatible = "fixed-clock";
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reg = <0>;
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#clock-cells = <0>;
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clock-frequency = <112400000>;
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};
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clk_32k: clock@1 {
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compatible = "fixed-clock";
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reg = <1>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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&tegra_car {
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clocks = <&clk_32k> <&osc>;
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};
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clock@60006000 {
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emc-timings-3 {
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nvidia,ram-code = <3>;
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timing-12750000 {
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clock-frequency = <12750000>;
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nvidia,parent-clock-frequency = <408000000>;
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clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
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clock-names = "emc-parent";
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};
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timing-20400000 {
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clock-frequency = <20400000>;
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nvidia,parent-clock-frequency = <408000000>;
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clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
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clock-names = "emc-parent";
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};
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};
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};
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};
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