124 lines
4.4 KiB
Plaintext
Executable file
124 lines
4.4 KiB
Plaintext
Executable file
Imagination Technologies Pistachio SoC clock controllers
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========================================================
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Pistachio has four clock controllers (core clock, peripheral clock, peripheral
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general control, and top general control) which are instantiated individually
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from the device-tree.
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External clocks:
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----------------
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There are three external inputs to the clock controllers which should be
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defined with the following clock-output-names:
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- "xtal": External 52Mhz oscillator (required)
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- "audio_clk_in": Alternate audio reference clock (optional)
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- "enet_clk_in": Alternate ethernet PHY clock (optional)
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Core clock controller:
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----------------------
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The core clock controller generates clocks for the CPU, RPU (WiFi + BT
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co-processor), audio, and several peripherals.
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Required properties:
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- compatible: Must be "img,pistachio-clk".
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- reg: Must contain the base address and length of the core clock controller.
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- #clock-cells: Must be 1. The single cell is the clock identifier.
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See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
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- clocks: Must contain an entry for each clock in clock-names.
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- clock-names: Must include "xtal" (see "External clocks") and
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"audio_clk_in_gate", "enet_clk_in_gate" which are generated by the
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top-level general control.
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Example:
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clk_core: clock-controller@18144000 {
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compatible = "img,pistachio-clk";
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reg = <0x18144000 0x800>;
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clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
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<&cr_top EXT_CLK_ENET_IN>;
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clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";
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#clock-cells = <1>;
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};
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Peripheral clock controller:
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----------------------------
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The peripheral clock controller generates clocks for the DDR, ROM, and other
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peripherals. The peripheral system clock ("periph_sys") generated by the core
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clock controller is the input clock to the peripheral clock controller.
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Required properties:
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- compatible: Must be "img,pistachio-periph-clk".
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- reg: Must contain the base address and length of the peripheral clock
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controller.
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- #clock-cells: Must be 1. The single cell is the clock identifier.
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See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
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- clocks: Must contain an entry for each clock in clock-names.
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- clock-names: Must include "periph_sys", the peripheral system clock generated
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by the core clock controller.
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Example:
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clk_periph: clock-controller@18144800 {
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compatible = "img,pistachio-clk-periph";
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reg = <0x18144800 0x800>;
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clocks = <&clk_core CLK_PERIPH_SYS>;
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clock-names = "periph_sys";
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#clock-cells = <1>;
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};
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Peripheral general control:
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---------------------------
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The peripheral general control block generates system interface clocks and
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resets for various peripherals. It also contains miscellaneous peripheral
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control registers. The system clock ("sys") generated by the peripheral clock
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controller is the input clock to the system clock controller.
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Required properties:
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- compatible: Must include "img,pistachio-periph-cr" and "syscon".
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- reg: Must contain the base address and length of the peripheral general
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control registers.
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- #clock-cells: Must be 1. The single cell is the clock identifier.
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See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
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- clocks: Must contain an entry for each clock in clock-names.
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- clock-names: Must include "sys", the system clock generated by the peripheral
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clock controller.
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Example:
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cr_periph: syscon@18144800 {
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compatible = "img,pistachio-cr-periph", "syscon";
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reg = <0x18148000 0x1000>;
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clocks = <&clock_periph PERIPH_CLK_PERIPH_SYS>;
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clock-names = "sys";
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#clock-cells = <1>;
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};
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Top-level general control:
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--------------------------
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The top-level general control block contains miscellaneous control registers and
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gates for the external clocks "audio_clk_in" and "enet_clk_in".
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Required properties:
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- compatible: Must include "img,pistachio-cr-top" and "syscon".
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- reg: Must contain the base address and length of the top-level
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control registers.
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- clocks: Must contain an entry for each clock in clock-names.
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- clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
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"External clocks").
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- #clock-cells: Must be 1. The single cell is the clock identifier.
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See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
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Example:
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cr_top: syscon@18144800 {
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compatible = "img,pistachio-cr-top", "syscon";
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reg = <0x18149000 0x200>;
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clocks = <&audio_refclk>, <&ext_enet_in>;
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clock-names = "audio_clk_in", "enet_clk_in";
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#clock-cells = <1>;
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};
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