59 lines
1.8 KiB
Plaintext
Executable file
59 lines
1.8 KiB
Plaintext
Executable file
* Rockchip RK3328 Clock and Reset Unit
|
|
|
|
The RK3328 clock controller generates and supplies clock to various
|
|
controllers within the SoC and also implements a reset controller for SoC
|
|
peripherals.
|
|
|
|
Required Properties:
|
|
|
|
- compatible: should be "rockchip,rk3328-cru"
|
|
- reg: physical base address of the controller and length of memory mapped
|
|
region.
|
|
- #clock-cells: should be 1.
|
|
- #reset-cells: should be 1.
|
|
|
|
Optional Properties:
|
|
|
|
- rockchip,grf: phandle to the syscon managing the "general register files"
|
|
If missing pll rates are not changeable, due to the missing pll lock status.
|
|
|
|
Each clock is assigned an identifier and client nodes can use this identifier
|
|
to specify the clock which they consume. All available clocks are defined as
|
|
preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
|
|
used in device tree sources. Similar macros exist for the reset sources in
|
|
these files.
|
|
|
|
External clocks:
|
|
|
|
There are several clocks that are generated outside the SoC. It is expected
|
|
that they are defined using standard clock bindings with following
|
|
clock-output-names:
|
|
- "xin24m" - crystal input - required,
|
|
- "clkin_i2s" - external I2S clock - optional,
|
|
- "gmac_clkin" - external GMAC clock - optional
|
|
- "phy_50m_out" - output clock of the pll in the mac phy
|
|
- "hdmi_phy" - output clock of the hdmi phy pll - optional
|
|
|
|
Example: Clock controller node:
|
|
|
|
cru: clock-controller@ff440000 {
|
|
compatible = "rockchip,rk3328-cru";
|
|
reg = <0x0 0xff440000 0x0 0x1000>;
|
|
rockchip,grf = <&grf>;
|
|
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
Example: UART controller node that consumes the clock generated by the clock
|
|
controller:
|
|
|
|
uart0: serial@ff120000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0xff120000 0x100>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&cru SCLK_UART0>;
|
|
};
|