72 lines
2 KiB
Plaintext
Executable file
72 lines
2 KiB
Plaintext
Executable file
STMicroelectronics STM32H7 Reset and Clock Controller
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=====================================================
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The RCC IP is both a reset and a clock controller.
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Please refer to clock-bindings.txt for common clock controller binding usage.
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Please also refer to reset.txt for common reset controller binding usage.
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Required properties:
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- compatible: Should be:
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"st,stm32h743-rcc"
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- reg: should be register base and length as documented in the
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datasheet
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- #reset-cells: 1, see below
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- #clock-cells : from common clock binding; shall be set to 1
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- clocks: External oscillator clock phandle
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- high speed external clock signal (HSE)
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- low speed external clock signal (LSE)
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- external I2S clock (I2S_CKIN)
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Optional properties:
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- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
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write protection (RTC clock).
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Example:
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rcc: reset-clock-controller@58024400 {
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compatible = "st,stm32h743-rcc", "st,stm32-rcc";
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reg = <0x58024400 0x400>;
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#reset-cells = <1>;
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#clock-cells = <1>;
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clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
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st,syscfg = <&pwrcfg>;
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};
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The peripheral clock consumer should specify the desired clock by
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having the clock ID in its "clocks" phandle cell.
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Example:
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timer5: timer@40000c00 {
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compatible = "st,stm32-timer";
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reg = <0x40000c00 0x400>;
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interrupts = <50>;
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clocks = <&rcc TIM5_CK>;
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};
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Specifying softreset control of devices
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=======================================
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Device nodes should specify the reset channel required in their "resets"
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property, containing a phandle to the reset device node and an index specifying
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which channel to use.
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The index is the bit number within the RCC registers bank, starting from RCC
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base address.
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It is calculated as: index = register_offset / 4 * 32 + bit_offset.
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Where bit_offset is the bit offset within the register.
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For example, for CRC reset:
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crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
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Example:
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timer2 {
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resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
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};
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