24 lines
708 B
Plaintext
Executable file
24 lines
708 B
Plaintext
Executable file
* Sigma Designs Tango4 Clock Generator
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The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used
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for RAM and various peripheral devices). The clock binding described here
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is applicable to all Tango4 SoCs.
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Required Properties:
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- compatible: should be "sigma,tango4-clkgen".
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- reg: physical base address of the device and length of memory mapped region.
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- clocks: phandle of the input clock (crystal oscillator).
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- clock-output-names: should be "cpuclk" and "sysclk".
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- #clock-cells: should be set to 1.
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Example:
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clkgen: clkgen@10000 {
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compatible = "sigma,tango4-clkgen";
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reg = <0x10000 0x40>;
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clocks = <&xtal>;
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clock-output-names = "cpuclk", "sysclk";
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#clock-cells = <1>;
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};
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