94 lines
2.9 KiB
Plaintext
Executable file
94 lines
2.9 KiB
Plaintext
Executable file
Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
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TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
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registers call CFGCHIPn. Some of these registers function as clock
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gates. This document describes the bindings for those clocks.
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All of the clock nodes described below must be child nodes of a CFGCHIP node
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(compatible = "ti,da830-cfgchip").
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USB PHY clocks
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--------------
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Required properties:
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- compatible: shall be "ti,da830-usb-phy-clocks".
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- #clock-cells: from common clock binding; shall be set to 1.
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- clocks: phandles to the parent clocks corresponding to clock-names
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- clock-names: shall be "fck", "usb_refclkin", "auxclk"
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This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
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clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
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eHRPWM Time Base Clock (TBCLK)
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------------------------------
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Required properties:
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- compatible: shall be "ti,da830-tbclksync".
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- #clock-cells: from common clock binding; shall be set to 0.
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- clocks: phandle to the parent clock
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- clock-names: shall be "fck"
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PLL DIV4.5 divider
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------------------
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Required properties:
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- compatible: shall be "ti,da830-div4p5ena".
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- #clock-cells: from common clock binding; shall be set to 0.
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- clocks: phandle to the parent clock
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- clock-names: shall be "pll0_pllout"
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EMIFA clock source (ASYNC1)
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---------------------------
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Required properties:
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- compatible: shall be "ti,da850-async1-clksrc".
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- #clock-cells: from common clock binding; shall be set to 0.
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- clocks: phandles to the parent clocks corresponding to clock-names
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- clock-names: shall be "pll0_sysclk3", "div4.5"
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ASYNC3 clock source
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-------------------
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Required properties:
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- compatible: shall be "ti,da850-async3-clksrc".
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- #clock-cells: from common clock binding; shall be set to 0.
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- clocks: phandles to the parent clocks corresponding to clock-names
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- clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"
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Examples:
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cfgchip: syscon@1417c {
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compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
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reg = <0x1417c 0x14>;
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usb_phy_clk: usb-phy-clocks {
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compatible = "ti,da830-usb-phy-clocks";
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#clock-cells = <1>;
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clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;
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clock-names = "fck", "usb_refclkin", "auxclk";
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};
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ehrpwm_tbclk: ehrpwm_tbclk {
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compatible = "ti,da830-tbclksync";
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#clock-cells = <0>;
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clocks = <&psc1 17>;
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clock-names = "fck";
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};
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div4p5_clk: div4.5 {
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compatible = "ti,da830-div4p5ena";
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#clock-cells = <0>;
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clocks = <&pll0_pllout>;
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clock-names = "pll0_pllout";
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};
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async1_clk: async1 {
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compatible = "ti,da850-async1-clksrc";
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#clock-cells = <0>;
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clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
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clock-names = "pll0_sysclk3", "div4.5";
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};
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async3_clk: async3 {
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compatible = "ti,da850-async3-clksrc";
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#clock-cells = <0>;
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clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
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clock-names = "pll0_sysclk2", "pll1_sysclk2";
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};
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};
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Also see:
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- Documentation/devicetree/bindings/clock/clock-bindings.txt
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