116 lines
3.9 KiB
Plaintext
Executable file
116 lines
3.9 KiB
Plaintext
Executable file
Amlogic specific extensions to the Synopsys Designware HDMI Controller
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======================================================================
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The Amlogic Meson Synopsys Designware Integration is composed of :
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- A Synopsys DesignWare HDMI Controller IP
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- A TOP control block controlling the Clocks and PHY
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- A custom HDMI PHY in order to convert video to TMDS signal
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___________________________________
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| HDMI TOP |<= HPD
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|___________________________________|
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| | |
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| Synopsys HDMI | HDMI PHY |=> TMDS
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| Controller |________________|
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|___________________________________|<=> DDC
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The HDMI TOP block only supports HPD sensing.
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The Synopsys HDMI Controller interrupt is routed through the
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TOP Block interrupt.
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Communication to the TOP Block and the Synopsys HDMI Controller is done
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via a pair of dedicated addr+read/write registers.
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The HDMI PHY is configured by registers in the HHI register block.
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Pixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux
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selects either the ENCI encoder for the 576i or 480i formats or the ENCP
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encoder for all the other formats including interlaced HD formats.
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The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
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DVI timings for the HDMI controller.
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Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
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HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
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audio source interfaces.
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Required properties:
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- compatible: value should be different for each SoC family as :
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- GXBB (S905) : "amlogic,meson-gxbb-dw-hdmi"
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- GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi"
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- GXM (S912) : "amlogic,meson-gxm-dw-hdmi"
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followed by the common "amlogic,meson-gx-dw-hdmi"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The HDMI interrupt number
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- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
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and the Amlogic Meson venci clocks as described in
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Documentation/devicetree/bindings/clock/clock-bindings.txt,
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the clocks are soc specific, the clock-names should be "iahb", "isfr", "venci"
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- resets, resets-names: must have the phandles to the HDMI apb, glue and phy
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resets as described in :
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Documentation/devicetree/bindings/reset/reset.txt,
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the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy"
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Optional properties:
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- hdmi-supply: Optional phandle to an external 5V regulator to power the HDMI
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logic, as described in the file ../regulator/regulator.txt
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Required nodes:
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The connections to the HDMI ports are modeled using the OF graph
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bindings specified in Documentation/devicetree/bindings/graph.txt.
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The following table lists for each supported model the port number
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corresponding to each HDMI output and input.
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Port 0 Port 1
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-----------------------------------------
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S905 (GXBB) VENC Input TMDS Output
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S905X (GXL) VENC Input TMDS Output
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S905D (GXL) VENC Input TMDS Output
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S912 (GXM) VENC Input TMDS Output
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Example:
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hdmi-connector {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&hdmi_tx_tmds_out>;
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};
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};
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};
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hdmi_tx: hdmi-tx@c883a000 {
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compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
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reg = <0x0 0xc883a000 0x0 0x1c>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
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resets = <&reset RESET_HDMITX_CAPB3>,
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<&reset RESET_HDMI_SYSTEM_RESET>,
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<&reset RESET_HDMI_TX>;
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reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
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clocks = <&clkc CLKID_HDMI_PCLK>,
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<&clkc CLKID_CLK81>,
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<&clkc CLKID_GCLK_VENCI_INT0>;
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clock-names = "isfr", "iahb", "venci";
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#address-cells = <1>;
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#size-cells = <0>;
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/* VPU VENC Input */
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hdmi_tx_venc_port: port@0 {
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reg = <0>;
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hdmi_tx_in: endpoint {
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remote-endpoint = <&hdmi_tx_out>;
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};
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};
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/* TMDS Output */
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hdmi_tx_tmds_port: port@1 {
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reg = <1>;
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hdmi_tx_tmds_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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};
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