121 lines
3.7 KiB
Plaintext
Executable file
121 lines
3.7 KiB
Plaintext
Executable file
ZTE VOU Display Controller
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This is a display controller found on ZTE ZX296718 SoC. It includes multiple
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Graphic Layer (GL) and Video Layer (VL), two Mixers/Channels, and a few blocks
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handling scaling, color space conversion etc. VOU also integrates the support
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for typical output devices, like HDMI, TV Encoder, VGA, and RGB LCD.
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* Master VOU node
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It must be the parent node of all the sub-device nodes.
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Required properties:
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- compatible: should be "zte,zx296718-vou"
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- #address-cells: should be <1>
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- #size-cells: should be <1>
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- ranges: list of address translations between VOU and sub-devices
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* VOU DPC device
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Required properties:
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- compatible: should be "zte,zx296718-dpc"
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- reg: Physical base address and length of DPC register regions, one for each
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entry in 'reg-names'
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- reg-names: The names of register regions. The following regions are required:
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"osd"
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"timing_ctrl"
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"dtrc"
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"vou_ctrl"
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"otfppu"
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- interrupts: VOU DPC interrupt number to CPU
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- clocks: A list of phandle + clock-specifier pairs, one for each entry
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in 'clock-names'
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- clock-names: A list of clock names. The following clocks are required:
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"aclk"
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"ppu_wclk"
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"main_wclk"
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"aux_wclk"
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* HDMI output device
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Required properties:
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- compatible: should be "zte,zx296718-hdmi"
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- reg: Physical base address and length of the HDMI device IO region
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- interrupts : HDMI interrupt number to CPU
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- clocks: A list of phandle + clock-specifier pairs, one for each entry
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in 'clock-names'
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- clock-names: A list of clock names. The following clocks are required:
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"osc_cec"
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"osc_clk"
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"xclk"
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* TV Encoder output device
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Required properties:
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- compatible: should be "zte,zx296718-tvenc"
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- reg: Physical base address and length of the TVENC device IO region
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- zte,tvenc-power-control: the phandle to SYSCTRL block followed by two
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integer cells. The first cell is the offset of SYSCTRL register used
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to control TV Encoder DAC power, and the second cell is the bit mask.
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* VGA output device
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Required properties:
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- compatible: should be "zte,zx296718-vga"
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- reg: Physical base address and length of the VGA device IO region
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- interrupts : VGA interrupt number to CPU
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- clocks: Phandle with clock-specifier pointing to VGA I2C clock.
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- clock-names: Must be "i2c_wclk".
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- zte,vga-power-control: the phandle to SYSCTRL block followed by two
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integer cells. The first cell is the offset of SYSCTRL register used
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to control VGA DAC power, and the second cell is the bit mask.
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Example:
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vou: vou@1440000 {
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compatible = "zte,zx296718-vou";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1440000 0x10000>;
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dpc: dpc@0 {
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compatible = "zte,zx296718-dpc";
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reg = <0x0000 0x1000>, <0x1000 0x1000>,
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<0x5000 0x1000>, <0x6000 0x1000>,
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<0xa000 0x1000>;
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reg-names = "osd", "timing_ctrl",
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"dtrc", "vou_ctrl",
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"otfppu";
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
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<&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
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clock-names = "aclk", "ppu_wclk",
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"main_wclk", "aux_wclk";
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};
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vga: vga@8000 {
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compatible = "zte,zx296718-vga";
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reg = <0x8000 0x1000>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topcrm VGA_I2C_WCLK>;
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clock-names = "i2c_wclk";
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zte,vga-power-control = <&sysctrl 0x170 0xe0>;
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};
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hdmi: hdmi@c000 {
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compatible = "zte,zx296718-hdmi";
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reg = <0xc000 0x4000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
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clocks = <&topcrm HDMI_OSC_CEC>,
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<&topcrm HDMI_OSC_CLK>,
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<&topcrm HDMI_XCLK>;
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clock-names = "osc_cec", "osc_clk", "xclk";
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};
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tvenc: tvenc@2000 {
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compatible = "zte,zx296718-tvenc";
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reg = <0x2000 0x1000>;
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zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
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};
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};
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