109 lines
3.5 KiB
Plaintext
Executable file
109 lines
3.5 KiB
Plaintext
Executable file
NVIDIA Tegra Boot and Power Management Processor (BPMP)
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The BPMP is a specific processor in Tegra chip, which is designed for
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booting process handling and offloading the power management, clock
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management, and reset control tasks from the CPU. The binding document
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defines the resources that would be used by the BPMP firmware driver,
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which can create the interprocessor communication (IPC) between the CPU
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and BPMP.
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Required properties:
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- name : Should be bpmp
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- compatible
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Array of strings
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One of:
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- "nvidia,tegra186-bpmp"
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- mboxes : The phandle of mailbox controller and the mailbox specifier.
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- shmem : List of the phandle of the TX and RX shared memory area that
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the IPC between CPU and BPMP is based on.
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- #clock-cells : Should be 1.
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- #power-domain-cells : Should be 1.
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- #reset-cells : Should be 1.
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This node is a mailbox consumer. See the following files for details of
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the mailbox subsystem, and the specifiers implemented by the relevant
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provider(s):
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- .../mailbox/mailbox.txt
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- .../mailbox/nvidia,tegra186-hsp.txt
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This node is a clock, power domain, and reset provider. See the following
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files for general documentation of those features, and the specifiers
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implemented by this node:
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- .../clock/clock-bindings.txt
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- <dt-bindings/clock/tegra186-clock.h>
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- ../power/power_domain.txt
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- <dt-bindings/power/tegra186-powergate.h>
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- .../reset/reset.txt
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- <dt-bindings/reset/tegra186-reset.h>
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The BPMP implements some services which must be represented by separate nodes.
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For example, it can provide access to certain I2C controllers, and the I2C
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bindings represent each I2C controller as a device tree node. Such nodes should
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be nested directly inside the main BPMP node.
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Software can determine whether a child node of the BPMP node represents a device
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by checking for a compatible property. Any node with a compatible property
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represents a device that can be instantiated. Nodes without a compatible
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property may be used to provide configuration information regarding the BPMP
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itself, although no such configuration nodes are currently defined by this
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binding.
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The BPMP firmware defines no single global name-/numbering-space for such
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services. Put another way, the numbering scheme for I2C buses is distinct from
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the numbering scheme for any other service the BPMP may provide (e.g. a future
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hypothetical SPI bus service). As such, child device nodes will have no reg
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property, and the BPMP node will have no #address-cells or #size-cells property.
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The shared memory bindings for BPMP
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-----------------------------------
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The shared memory area for the IPC TX and RX between CPU and BPMP are
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predefined and work on top of sysram, which is an SRAM inside the chip.
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See ".../sram/sram.txt" for the bindings.
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Example:
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hsp_top0: hsp@3c00000 {
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...
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#mbox-cells = <2>;
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};
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sysram@30000000 {
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compatible = "nvidia,tegra186-sysram", "mmio-sram";
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reg = <0x0 0x30000000 0x0 0x50000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
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cpu_bpmp_tx: shmem@4e000 {
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compatible = "nvidia,tegra186-bpmp-shmem";
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reg = <0x0 0x4e000 0x0 0x1000>;
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label = "cpu-bpmp-tx";
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pool;
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};
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cpu_bpmp_rx: shmem@4f000 {
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compatible = "nvidia,tegra186-bpmp-shmem";
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reg = <0x0 0x4f000 0x0 0x1000>;
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label = "cpu-bpmp-rx";
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pool;
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};
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};
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bpmp {
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compatible = "nvidia,tegra186-bpmp";
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mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
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shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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i2c {
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compatible = "...";
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...
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};
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};
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