40 lines
1.3 KiB
Plaintext
Executable file
40 lines
1.3 KiB
Plaintext
Executable file
Keystone 2 DSP GPIO controller bindings
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HOST OS userland running on ARM can send interrupts to DSP cores using
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the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
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This is one of the component used by the IPC mechanism used on Keystone SOCs.
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For example TCI6638K2K SoC has 8 DSP GPIO controllers:
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- 8 for C66x CorePacx CPUs 0-7
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Keystone 2 DSP GPIO controller has specific features:
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- each GPIO can be configured only as output pin;
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- setting GPIO value to 1 causes IRQ generation on target DSP core;
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- reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
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pending.
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Required Properties:
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- compatible: should be "ti,keystone-dsp-gpio"
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- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
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access device state control registers and the offset of device's specific
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registers within device state control registers range.
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- gpio-controller: Marks the device node as a gpio controller.
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- #gpio-cells: Should be 2.
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Please refer to gpio.txt in this directory for details of the common GPIO
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bindings used by client devices.
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Example:
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dspgpio0: keystone_dsp_gpio@2620240 {
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compatible = "ti,keystone-dsp-gpio";
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ti,syscon-dev = <&devctrl 0x240>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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dsp0: dsp0 {
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compatible = "linux,rproc-user";
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...
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kick-gpio = <&dspgpio0 27>;
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};
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