36 lines
1.5 KiB
Plaintext
Executable file
36 lines
1.5 KiB
Plaintext
Executable file
Mediatek MT7621 SoC GPIO controller bindings
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The IP core used inside these SoCs has 3 banks of 32 GPIOs each.
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The registers of all the banks are interwoven inside one single IO range.
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We load one GPIO controller instance per bank. Also the GPIO controller can receive
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interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU
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using GIC INT12.
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Required properties for the top level node:
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- #gpio-cells : Should be two. The first cell is the GPIO pin number and the
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second cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
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Only the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt. Should be 2. The first cell defines the interrupt number,
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the second encodes the triger flags encoded as described in
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Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
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- compatible:
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- "mediatek,mt7621-gpio" for Mediatek controllers
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- reg : Physical base address and length of the controller's registers
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- interrupt-parent : phandle of the parent interrupt controller.
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- interrupts : Interrupt specifier for the controllers interrupt.
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- interrupt-controller : Mark the device node as an interrupt controller.
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- gpio-controller : Marks the device node as a GPIO controller.
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Example:
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gpio@600 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "mediatek,mt7621-gpio";
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gpio-controller;
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interrupt-controller;
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reg = <0x600 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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