50 lines
1.8 KiB
Plaintext
Executable file
50 lines
1.8 KiB
Plaintext
Executable file
=== ST Microelectronics SPEAr SPI CS Driver ===
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SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
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Cell spi controller through its system registers, which otherwise remains under
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PL022 control. If chipselect remain under PL022 control then they would be
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released as soon as transfer is over and TxFIFO becomes empty. This is not
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desired by some of the device protocols above spi which expect (multiple)
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transfers without releasing their chipselects.
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Chipselects can be controlled by software by turning them as GPIOs. SPEAr
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provides another interface through system registers through which software can
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directly control each PL022 chipselect. Hence, it is natural for SPEAr to export
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the control of this interface as gpio.
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Required properties:
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* compatible: should be defined as "st,spear-spics-gpio"
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* reg: mentioning address range of spics controller
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* st-spics,peripcfg-reg: peripheral configuration register offset
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* st-spics,sw-enable-bit: bit offset to enable sw control
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* st-spics,cs-value-bit: bit offset to drive chipselect low or high
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* st-spics,cs-enable-mask: chip select number bit mask
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* st-spics,cs-enable-shift: chip select number program offset
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* gpio-controller: Marks the device node as gpio controller
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* #gpio-cells: should be 1 and will mention chip select number
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All the above bit offsets are within peripcfg register.
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Example:
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-------
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spics: spics@e0700000{
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compatible = "st,spear-spics-gpio";
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reg = <0xe0700000 0x1000>;
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st-spics,peripcfg-reg = <0x3b0>;
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st-spics,sw-enable-bit = <12>;
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st-spics,cs-value-bit = <11>;
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st-spics,cs-enable-mask = <3>;
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st-spics,cs-enable-shift = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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spi0: spi@e0100000 {
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num-cs = <3>;
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cs-gpios = <&gpio1 7 0>, <&spics 0>,
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<&spics 1>;
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...
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}
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