45 lines
1.8 KiB
Plaintext
Executable file
45 lines
1.8 KiB
Plaintext
Executable file
* SPEAr Shared IRQ layer (shirq)
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SPEAr3xx architecture includes shared/multiplexed irqs for certain set
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of devices. The multiplexor provides a single interrupt to parent
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interrupt controller (VIC) on behalf of a group of devices.
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There can be multiple groups available on SPEAr3xx variants but not
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exceeding 4. The number of devices in a group can differ, further they
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may share same set of status/mask registers spanning across different
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bit masks. Also in some cases the group may not have enable or other
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registers. This makes software little complex.
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A single node in the device tree is used to describe the shared
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interrupt multiplexor (one node for all groups). A group in the
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interrupt controller shares config/control registers with other groups.
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For example, a 32-bit interrupt enable/disable config register can
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accommodate up to 4 interrupt groups.
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Required properties:
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- compatible: should be, either of
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- "st,spear300-shirq"
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- "st,spear310-shirq"
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- "st,spear320-shirq"
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- interrupt-controller: Identifies the node as an interrupt controller.
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- #interrupt-cells: should be <1> which basically contains the offset
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(starting from 0) of interrupts for all the groups.
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- reg: Base address and size of shirq registers.
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- interrupts: The list of interrupts generated by the groups which are
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then connected to a parent interrupt controller. Each group is
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associated with one of the interrupts, hence number of interrupts (to
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parent) is equal to number of groups. The format of the interrupt
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specifier depends in the interrupt parent controller.
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Example:
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The following is an example from the SPEAr320 SoC dtsi file.
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shirq: interrupt-controller@b3000000 {
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compatible = "st,spear320-shirq";
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reg = <0xb3000000 0x1000>;
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interrupts = <28 29 30 1>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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