60 lines
2.2 KiB
Plaintext
Executable file
60 lines
2.2 KiB
Plaintext
Executable file
OMAP2+ IOMMU
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Required properties:
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- compatible : Should be one of,
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"ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
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"ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
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"ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
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"ti,dra7-iommu" for DRA7xx IOMMU instances
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- ti,hwmods : Name of the hwmod associated with the IOMMU instance
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- reg : Address space for the configuration registers
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- interrupts : Interrupt specifier for the IOMMU instance
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- #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
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and needs no additional data in the pargs specifier. Please
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also refer to the generic bindings document for more info
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on this property,
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Documentation/devicetree/bindings/iommu/iommu.txt
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Optional properties:
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- ti,#tlb-entries : Number of entries in the translation look-aside buffer.
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Should be either 8 or 32 (default: 32)
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- ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing
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back a bus error response on MMU faults.
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- ti,syscon-mmuconfig : Should be a pair of the phandle to the DSP_SYSTEM
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syscon node that contains the additional control
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register for enabling the MMU, and the MMU instance
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number (0-indexed) within the sub-system. This property
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is required for DSP IOMMU instances on DRA7xx SoCs. The
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instance number should be 0 for DSP MDMA MMUs and 1 for
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DSP EDMA MMUs.
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Example:
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/* OMAP3 ISP MMU */
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mmu_isp: mmu@480bd400 {
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#iommu-cells = <0>;
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compatible = "ti,omap2-iommu";
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reg = <0x480bd400 0x80>;
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interrupts = <24>;
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ti,hwmods = "mmu_isp";
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ti,#tlb-entries = <8>;
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};
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/* DRA74x DSP2 MMUs */
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mmu0_dsp2: mmu@41501000 {
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compatible = "ti,dra7-dsp-iommu";
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reg = <0x41501000 0x100>;
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mmu0_dsp2";
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#iommu-cells = <0>;
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ti,syscon-mmuconfig = <&dsp2_system 0x0>;
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};
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mmu1_dsp2: mmu@41502000 {
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compatible = "ti,dra7-dsp-iommu";
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reg = <0x41502000 0x100>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mmu1_dsp2";
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#iommu-cells = <0>;
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ti,syscon-mmuconfig = <&dsp2_system 0x1>;
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};
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