214 lines
8 KiB
Plaintext
Executable file
214 lines
8 KiB
Plaintext
Executable file
Renesas R-Car Video Input driver (rcar_vin)
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-------------------------------------------
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The rcar_vin device provides video input capabilities for the Renesas R-Car
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family of devices.
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Each VIN instance has a single parallel input that supports RGB and YUV video,
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with both external synchronization and BT.656 synchronization for the latter.
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Depending on the instance the VIN input is connected to external SoC pins, or
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on Gen3 platforms to a CSI-2 receiver.
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- compatible: Must be one or more of the following
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- "renesas,vin-r8a7743" for the R8A7743 device
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- "renesas,vin-r8a7745" for the R8A7745 device
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- "renesas,vin-r8a7778" for the R8A7778 device
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- "renesas,vin-r8a7779" for the R8A7779 device
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- "renesas,vin-r8a7790" for the R8A7790 device
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- "renesas,vin-r8a7791" for the R8A7791 device
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- "renesas,vin-r8a7792" for the R8A7792 device
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- "renesas,vin-r8a7793" for the R8A7793 device
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- "renesas,vin-r8a7794" for the R8A7794 device
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- "renesas,vin-r8a7795" for the R8A7795 device
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- "renesas,vin-r8a7796" for the R8A7796 device
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- "renesas,vin-r8a77965" for the R8A77965 device
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- "renesas,vin-r8a77970" for the R8A77970 device
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- "renesas,vin-r8a77995" for the R8A77995 device
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- "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible
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device.
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When compatible with the generic version nodes must list the
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SoC-specific version corresponding to the platform first
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followed by the generic version.
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- reg: the register base and size for the device registers
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- interrupts: the interrupt for the device
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- clocks: Reference to the parent clock
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Additionally, an alias named vinX will need to be created to specify
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which video input device this is.
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The per-board settings Gen2 platforms:
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- port - sub-node describing a single endpoint connected to the VIN
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from external SoC pins as described in video-interfaces.txt[1].
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Only the first one will be considered as each vin interface has one
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input port.
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- Optional properties for endpoint nodes:
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- hsync-active: see [1] for description. Default is active high.
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- vsync-active: see [1] for description. Default is active high.
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If both HSYNC and VSYNC polarities are not specified, embedded
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synchronization is selected.
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- field-active-even: see [1] for description. Default is active high.
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- bus-width: see [1] for description. The selected bus width depends on
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the SoC type and selected input image format.
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Valid values are: 8, 10, 12, 16, 24 and 32.
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- data-shift: see [1] for description. Valid values are 0 and 8.
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- data-enable-active: polarity of CLKENB signal, see [1] for
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description. Default is active high.
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The per-board settings Gen3 platforms:
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Gen3 platforms can support both a single connected parallel input source
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from external SoC pins (port@0) and/or multiple parallel input sources
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from local SoC CSI-2 receivers (port@1) depending on SoC.
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- renesas,id - ID number of the VIN, VINx in the documentation.
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- ports
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- port@0 - sub-node describing a single endpoint connected to the VIN
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from external SoC pins as described in video-interfaces.txt[1].
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Describing more than one endpoint in port@0 is invalid. Only VIN
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instances that are connected to external pins should have port@0.
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Endpoint nodes of port@0 support the optional properties listed in
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the Gen2 per-board settings description.
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- port@1 - sub-nodes describing one or more endpoints connected to
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the VIN from local SoC CSI-2 receivers. The endpoint numbers must
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use the following schema.
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- endpoint@0 - sub-node describing the endpoint connected to CSI20
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- endpoint@1 - sub-node describing the endpoint connected to CSI21
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- endpoint@2 - sub-node describing the endpoint connected to CSI40
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- endpoint@3 - sub-node describing the endpoint connected to CSI41
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Endpoint nodes of port@1 do not support any optional endpoint property.
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Device node example for Gen2 platforms
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--------------------------------------
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aliases {
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vin0 = &vin0;
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};
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vin0: vin@e6ef0000 {
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compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
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clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
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reg = <0 0xe6ef0000 0 0x1000>;
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interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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Board setup example for Gen2 platforms (vin1 composite video input)
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-------------------------------------------------------------------
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&i2c2 {
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status = "okay";
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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adv7180@20 {
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compatible = "adi,adv7180";
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reg = <0x20>;
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remote = <&vin1>;
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port {
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adv7180: endpoint {
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bus-width = <8>;
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remote-endpoint = <&vin1ep0>;
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};
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};
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};
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};
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/* composite video input */
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&vin1 {
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pinctrl-0 = <&vin1_pins>;
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pinctrl-names = "default";
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status = "okay";
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port {
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vin1ep0: endpoint {
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remote-endpoint = <&adv7180>;
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bus-width = <8>;
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};
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};
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};
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Device node example for Gen3 platforms
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--------------------------------------
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vin0: video@e6ef0000 {
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compatible = "renesas,vin-r8a7795";
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reg = <0 0xe6ef0000 0 0x1000>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 811>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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resets = <&cpg 811>;
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renesas,id = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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vin0csi20: endpoint@0 {
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reg = <0>;
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remote-endpoint= <&csi20vin0>;
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};
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vin0csi21: endpoint@1 {
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reg = <1>;
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remote-endpoint= <&csi21vin0>;
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};
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vin0csi40: endpoint@2 {
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reg = <2>;
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remote-endpoint= <&csi40vin0>;
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};
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};
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};
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};
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csi20: csi2@fea80000 {
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compatible = "renesas,r8a7795-csi2";
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reg = <0 0xfea80000 0 0x10000>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 714>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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resets = <&cpg 714>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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csi20_in: endpoint {
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clock-lanes = <0>;
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data-lanes = <1>;
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remote-endpoint = <&adv7482_txb>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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csi20vin0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vin0csi20>;
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};
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};
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};
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};
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[1] video-interfaces.txt common video media interface
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