128 lines
3.6 KiB
Plaintext
Executable file
128 lines
3.6 KiB
Plaintext
Executable file
* Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller
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Required properties:
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- compatible: Must be "arm,primecell" and exactly one from
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"arm,pl172", "arm,pl175" or "arm,pl176".
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- reg: Must contains offset/length value for controller.
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- #address-cells: Must be 2. The partition number has to be encoded in the
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first address cell and it may accept values 0..N-1
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(N - total number of partitions). The second cell is the
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offset into the partition.
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- #size-cells: Must be set to 1.
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- ranges: Must contain one or more chip select memory regions.
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- clocks: Must contain references to controller clocks.
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- clock-names: Must contain "mpmcclk" and "apb_pclk".
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- clock-ranges: Empty property indicating that child nodes can inherit
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named clocks. Required only if clock tree data present
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in device tree.
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See clock-bindings.txt
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Child chip-select (cs) nodes contain the memory devices nodes connected to
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such as NOR (e.g. cfi-flash) and NAND.
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Required child cs node properties:
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- #address-cells: Must be 2.
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- #size-cells: Must be 1.
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- ranges: Empty property indicating that child nodes can inherit
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memory layout.
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- clock-ranges: Empty property indicating that child nodes can inherit
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named clocks. Required only if clock tree data present
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in device tree.
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- mpmc,cs: Chip select number. Indicates to the pl0172 driver
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which chipselect is used for accessing the memory.
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- mpmc,memory-width: Width of the chip select memory. Must be equal to
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either 8, 16 or 32.
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Optional child cs node config properties:
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- mpmc,async-page-mode: Enable asynchronous page mode.
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- mpmc,cs-active-high: Set chip select polarity to active high.
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- mpmc,byte-lane-low: Set byte lane state to low.
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- mpmc,extended-wait: Enable extended wait.
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- mpmc,buffer-enable: Enable write buffer, option is not supported by
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PL175 and PL176 controllers.
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- mpmc,write-protect: Enable write protect.
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Optional child cs node timing properties:
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- mpmc,write-enable-delay: Delay from chip select assertion to write
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enable (WE signal) in nano seconds.
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- mpmc,output-enable-delay: Delay from chip select assertion to output
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enable (OE signal) in nano seconds.
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- mpmc,write-access-delay: Delay from chip select assertion to write
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access in nano seconds.
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- mpmc,read-access-delay: Delay from chip select assertion to read
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access in nano seconds.
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- mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential
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accesses in nano seconds.
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- mpmc,turn-round-delay: Delay between access to memory banks in nano
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seconds.
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If any of the above timing parameters are absent, current parameter value will
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be taken from the corresponding HW reg.
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Example for pl172 with nor flash on chip select 0 shown below.
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emc: memory-controller@40005000 {
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compatible = "arm,pl172", "arm,primecell";
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reg = <0x40005000 0x1000>;
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clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
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clock-names = "mpmcclk", "apb_pclk";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x1c000000 0x1000000
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1 0 0x1d000000 0x1000000
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2 0 0x1e000000 0x1000000
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3 0 0x1f000000 0x1000000>;
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cs0 {
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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mpmc,cs = <0>;
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mpmc,memory-width = <16>;
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mpmc,byte-lane-low;
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mpmc,write-enable-delay = <0>;
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mpmc,output-enable-delay = <0>;
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mpmc,read-enable-delay = <70>;
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mpmc,page-mode-read-delay = <70>;
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flash@0,0 {
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compatible = "sst,sst39vf320", "cfi-flash";
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reg = <0 0 0x400000>;
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bank-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "data";
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reg = <0 0x400000>;
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};
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};
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};
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};
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