84 lines
2.2 KiB
Plaintext
Executable file
84 lines
2.2 KiB
Plaintext
Executable file
Imagination University Program MIPSfpga
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=======================================
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Under the Imagination University Program, a microAptiv UP core has been
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released for academic usage.
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As we are dealing with a MIPS core instantiated on an FPGA, specifications
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are fluid and can be varied in RTL.
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This binding document is provided as baseline guidance for the example
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project provided by IMG.
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The example project runs on the Nexys4DDR board by Digilent powered by
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the ARTIX-7 FPGA by Xilinx.
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Relevant details about the example project and the Nexys4DDR board:
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- microAptiv UP core m14Kc
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- 50MHz clock speed
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- 128Mbyte DDR RAM at 0x0000_0000
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- 8Kbyte RAM at 0x1000_0000
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- axi_intc at 0x1020_0000
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- axi_uart16550 at 0x1040_0000
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- axi_gpio at 0x1060_0000
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- axi_i2c at 0x10A0_0000
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- custom_gpio at 0x10C0_0000
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- axi_ethernetlite at 0x10E0_0000
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- 8Kbyte BootRAM at 0x1FC0_0000
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Required properties:
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--------------------
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- compatible: Must include "digilent,nexys4ddr","img,xilfpga".
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CPU nodes:
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----------
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A "cpus" node is required. Required properties:
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- #address-cells: Must be 1.
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- #size-cells: Must be 0.
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A CPU sub-node is also required for at least CPU 0. Required properties:
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- device_type: Must be "cpu".
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- compatible: Must be "mips,m14Kc".
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- reg: Must be <0>.
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- clocks: phandle to ext clock for fixed-clock received by MIPS core.
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Example:
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compatible = "img,xilfpga","digilent,nexys4ddr";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "mips,m14Kc";
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reg = <0>;
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clocks = <&ext>;
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};
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};
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ext: ext {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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Boot protocol:
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--------------
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The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
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This is for easy reprogrammibility via JTAG.
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The BootRAM initializes the cache and the axi_uart peripheral.
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DDR initialization is already handled by a HW IP block.
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When the example project bitstream is loaded, the cpu_reset button
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needs to be pressed.
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The bootram initializes the cache and axi_uart.
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Then outputs MIPSFPGA\n\r on the serial port on the Nexys4DDR board.
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At this point, the board is ready to load the Linux kernel
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vmlinux file via JTAG.
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