52 lines
1.6 KiB
Plaintext
Executable file
52 lines
1.6 KiB
Plaintext
Executable file
* Aspeed Firmware Memory controller
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* Aspeed SPI Flash Memory Controller
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The Firmware Memory Controller in the Aspeed AST2500 SoC supports
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three chip selects, two of which are always of SPI type and the third
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can be SPI or NOR type flash. These bindings only describe SPI.
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The two SPI flash memory controllers in the AST2500 each support two
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chip selects.
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Required properties:
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- compatible : Should be one of
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"aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
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"aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
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"aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
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"aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
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- reg : the first contains the control register location and length,
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the second contains the memory window mapping address and length
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- #address-cells : must be 1 corresponding to chip select child binding
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- #size-cells : must be 0 corresponding to chip select child binding
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Optional properties:
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- interrupts : Should contain the interrupt for the dma device if an
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FMC
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The child nodes are the SPI flash modules which must have a compatible
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property as specified in bindings/mtd/jedec,spi-nor.txt
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Optionally, the child node can contain properties for SPI mode (may be
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ignored):
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- spi-max-frequency - max frequency of spi bus
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Example:
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fmc: fmc@1e620000 {
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compatible = "aspeed,ast2500-fmc";
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reg = < 0x1e620000 0x94
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0x20000000 0x02000000 >;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <19>;
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flash@0 {
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reg = < 0 >;
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compatible = "jedec,spi-nor";
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/* spi-max-frequency = <>; */
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/* m25p,fast-read; */
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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