148 lines
5.3 KiB
Plaintext
Executable file
148 lines
5.3 KiB
Plaintext
Executable file
Device tree bindings for GPMC connected NANDs
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GPMC connected NAND (found on OMAP boards) are represented as child nodes of
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the GPMC controller with a name of "nand".
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All timing relevant properties as well as generic gpmc child properties are
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explained in a separate documents - please refer to
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Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
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For NAND specific properties such as ECC modes or bus width, please refer to
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Documentation/devicetree/bindings/mtd/nand.txt
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Required properties:
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- compatible: "ti,omap2-nand"
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- reg: range id (CS number), base offset and length of the
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NAND I/O space
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- interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
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Optional properties:
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- nand-bus-width: Set this numeric value to 16 if the hardware
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is wired that way. If not specified, a bus
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width of 8 is assumed.
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- ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
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"sw" 1-bit Hamming ecc code via software
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"hw" <deprecated> use "ham1" instead
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"hw-romcode" <deprecated> use "ham1" instead
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"ham1" 1-bit Hamming ecc code
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"bch4" 4-bit BCH ecc code
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"bch8" 8-bit BCH ecc code
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"bch16" 16-bit BCH ECC code
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Refer below "How to select correct ECC scheme for your device ?"
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- ti,nand-xfer-type: A string setting the data transfer type. One of:
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"prefetch-polled" Prefetch polled mode (default)
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"polled" Polled mode, without prefetch
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"prefetch-dma" Prefetch enabled DMA mode
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"prefetch-irq" Prefetch enabled irq mode
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- elm_id: <deprecated> use "ti,elm-id" instead
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- ti,elm-id: Specifies phandle of the ELM devicetree node.
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ELM is an on-chip hardware engine on TI SoC which is used for
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locating ECC errors for BCHx algorithms. SoC devices which have
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ELM hardware engines should specify this device node in .dtsi
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Using ELM for ECC error correction frees some CPU cycles.
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- rb-gpios: GPIO specifier for the ready/busy# pin.
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For inline partition table parsing (optional):
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- #address-cells: should be set to 1
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- #size-cells: should be set to 1
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Example for an AM33xx board:
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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reg = <0x50000000 0x36c>;
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interrupts = <100>;
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x1000000>; /* CS0 space, 16MB */
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elm_id = <&elm>;
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interrupt-controller;
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#interrupt-cells = <2>;
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, NAND I/O window 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>;
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nand-bus-width = <16>;
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ti,nand-ecc-opt = "bch8";
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ti,nand-xfer-type = "polled";
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rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <44>;
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gpmc,cs-wr-off-ns = <44>;
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gpmc,adv-on-ns = <6>;
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gpmc,adv-rd-off-ns = <34>;
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gpmc,adv-wr-off-ns = <44>;
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gpmc,we-off-ns = <40>;
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gpmc,oe-off-ns = <54>;
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* partitions go here */
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};
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};
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How to select correct ECC scheme for your device ?
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--------------------------------------------------
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Higher ECC scheme usually means better protection against bit-flips and
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increased system lifetime. However, selection of ECC scheme is dependent
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on various other factors also like;
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(1) support of built in hardware engines.
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Some legacy OMAP SoC do not have ELM harware engine, so those SoC cannot
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support ecc-schemes with hardware error-correction (BCHx_HW). However
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such SoC can use ecc-schemes with software library for error-correction
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(BCHx_HW_DETECTION_SW). The error correction capability with software
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library remains equivalent to their hardware counter-part, but there is
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slight CPU penalty when too many bit-flips are detected during reads.
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(2) Device parameters like OOBSIZE.
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Other factor which governs the selection of ecc-scheme is oob-size.
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Higher ECC schemes require more OOB/Spare area to store ECC syndrome,
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so the device should have enough free bytes available its OOB/Spare
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area to accommodate ECC for entire page. In general following expression
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helps in determining if given device can accommodate ECC syndrome:
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"2 + (PAGESIZE / 512) * ECC_BYTES" >= OOBSIZE"
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where
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OOBSIZE number of bytes in OOB/spare area
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PAGESIZE number of bytes in main-area of device page
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ECC_BYTES number of ECC bytes generated to protect
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512 bytes of data, which is:
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'3' for HAM1_xx ecc schemes
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'7' for BCH4_xx ecc schemes
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'14' for BCH8_xx ecc schemes
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'26' for BCH16_xx ecc schemes
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Example(a): For a device with PAGESIZE = 2048 and OOBSIZE = 64 and
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trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
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Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
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which is greater than capacity of NAND device (OOBSIZE=64)
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Hence, BCH16 cannot be supported on given device. But it can
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probably use lower ecc-schemes like BCH8.
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Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and
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trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
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Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
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which can be accommodated in the OOB/Spare area of this device
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(OOBSIZE=128). So this device can use BCH16 ecc-scheme.
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