59 lines
1.8 KiB
Plaintext
Executable file
59 lines
1.8 KiB
Plaintext
Executable file
* NXP SPI Flash Interface (SPIFI)
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NXP SPIFI is a specialized SPI interface for serial Flash devices.
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It supports one Flash device with 1-, 2- and 4-bits width in SPI
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mode 0 or 3. The controller operates in either command or memory
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mode. In memory mode the Flash is accessible from the CPU as
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normal memory.
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Required properties:
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- compatible : Should be "nxp,lpc1773-spifi"
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- reg : the first contains the register location and length,
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the second contains the memory mapping address and length
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- reg-names: Should contain the reg names "spifi" and "flash"
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- interrupts : Should contain the interrupt for the device
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- clocks : The clocks needed by the SPIFI controller
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- clock-names : Should contain the clock names "spifi" and "reg"
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Optional properties:
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- resets : phandle + reset specifier
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The SPI Flash must be a child of the SPIFI node and must have a
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compatible property as specified in bindings/mtd/jedec,spi-nor.txt
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Optionally it can also contain the following properties.
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- spi-cpol : Controller only supports mode 0 and 3 so either
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both spi-cpol and spi-cpha should be present or
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none of them
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- spi-cpha : See above
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- spi-rx-bus-width : Used to select how many pins that are used
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for input on the controller
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See bindings/spi/spi-bus.txt for more information.
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Example:
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spifi: spifi@40003000 {
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compatible = "nxp,lpc1773-spifi";
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reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
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reg-names = "spifi", "flash";
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interrupts = <30>;
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clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
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clock-names = "spifi", "reg";
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resets = <&rgu 53>;
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-cpol;
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spi-cpha;
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spi-rx-bus-width = <4>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "data";
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reg = <0 0x200000>;
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};
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};
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};
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