111 lines
2.1 KiB
Plaintext
Executable file
111 lines
2.1 KiB
Plaintext
Executable file
* Qualcomm Atheros QCA8xxx switch family
|
|
|
|
Required properties:
|
|
|
|
- compatible: should be one of:
|
|
"qca,qca8334"
|
|
"qca,qca8337"
|
|
|
|
- #size-cells: must be 0
|
|
- #address-cells: must be 1
|
|
|
|
Subnodes:
|
|
|
|
The integrated switch subnode should be specified according to the binding
|
|
described in dsa/dsa.txt. As the QCA8K switches do not have a N:N mapping of
|
|
port and PHY id, each subnode describing a port needs to have a valid phandle
|
|
referencing the internal PHY connected to it. The CPU port of this switch is
|
|
always port 0.
|
|
|
|
A CPU port node has the following optional node:
|
|
|
|
- fixed-link : Fixed-link subnode describing a link to a non-MDIO
|
|
managed entity. See
|
|
Documentation/devicetree/bindings/net/fixed-link.txt
|
|
for details.
|
|
|
|
For QCA8K the 'fixed-link' sub-node supports only the following properties:
|
|
|
|
- 'speed' (integer, mandatory), to indicate the link speed. Accepted
|
|
values are 10, 100 and 1000
|
|
- 'full-duplex' (boolean, optional), to indicate that full duplex is
|
|
used. When absent, half duplex is assumed.
|
|
|
|
Example:
|
|
|
|
|
|
&mdio0 {
|
|
phy_port1: phy@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
phy_port2: phy@1 {
|
|
reg = <1>;
|
|
};
|
|
|
|
phy_port3: phy@2 {
|
|
reg = <2>;
|
|
};
|
|
|
|
phy_port4: phy@3 {
|
|
reg = <3>;
|
|
};
|
|
|
|
phy_port5: phy@4 {
|
|
reg = <4>;
|
|
};
|
|
|
|
switch0@0 {
|
|
compatible = "qca,qca8337";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <0>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@0 {
|
|
reg = <0>;
|
|
label = "cpu";
|
|
ethernet = <&gmac1>;
|
|
phy-mode = "rgmii";
|
|
fixed-link {
|
|
speed = 1000;
|
|
full-duplex;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
label = "lan1";
|
|
phy-handle = <&phy_port1>;
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
label = "lan2";
|
|
phy-handle = <&phy_port2>;
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
label = "lan3";
|
|
phy-handle = <&phy_port3>;
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
label = "lan4";
|
|
phy-handle = <&phy_port4>;
|
|
};
|
|
|
|
port@5 {
|
|
reg = <5>;
|
|
label = "wan";
|
|
phy-handle = <&phy_port5>;
|
|
};
|
|
};
|
|
};
|
|
};
|