71 lines
2.4 KiB
Plaintext
Executable file
71 lines
2.4 KiB
Plaintext
Executable file
* Synopsys DesignWare PCIe interface
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Required properties:
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- compatible:
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"snps,dw-pcie" for RC mode;
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"snps,dw-pcie-ep" for EP mode;
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- reg: Should contain the configuration address space.
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- reg-names: Must be "config" for the PCIe configuration space.
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(The old way of getting the configuration address space from "ranges"
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is deprecated and should be avoided.)
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- num-lanes: number of lanes to use
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RC mode:
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- device_type: set to "pci"
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- ranges: ranges for the PCI memory and I/O regions
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- #interrupt-cells: set to <1>
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- interrupt-map-mask and interrupt-map: standard PCI
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properties to define the mapping of the PCIe interface to interrupt
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numbers.
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EP mode:
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- num-ib-windows: number of inbound address translation windows
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- num-ob-windows: number of outbound address translation windows
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Optional properties:
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- num-lanes: number of lanes to use (this property should be specified unless
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the link is brought already up in BIOS)
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- reset-gpio: GPIO pin number of power good signal
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- "pcie"
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- "pcie_bus"
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RC mode:
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- num-viewport: number of view ports configured in hardware. If a platform
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does not specify it, the driver assumes 2.
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- bus-range: PCI bus numbers covered (it is recommended for new devicetrees
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to specify this property, to keep backwards compatibility a range of
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0x00-0xff is assumed if not present)
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EP mode:
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- max-functions: maximum number of functions that can be configured
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Example configuration:
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pcie: pcie@dfc00000 {
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compatible = "snps,dw-pcie";
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reg = <0xdfc00000 0x0001000>, /* IP registers */
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<0xd0000000 0x0002000>; /* Configuration space */
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reg-names = "dbi", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
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0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
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interrupts = <25>, <24>;
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#interrupt-cells = <1>;
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num-lanes = <1>;
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};
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or
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pcie: pcie@dfc00000 {
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compatible = "snps,dw-pcie-ep";
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reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
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<0xdfc01000 0x0001000>, /* IP registers 2 */
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<0xd0000000 0x2000000>; /* Configuration space */
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reg-names = "dbi", "dbi2", "addr_space";
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num-ib-windows = <6>;
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num-ob-windows = <2>;
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num-lanes = <1>;
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};
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