136 lines
4.9 KiB
Plaintext
Executable file
136 lines
4.9 KiB
Plaintext
Executable file
* Rockchip AXI PCIe Root Port Bridge DT description
|
|
|
|
Required properties:
|
|
- #address-cells: Address representation for root ports, set to <3>
|
|
- #size-cells: Size representation for root ports, set to <2>
|
|
- #interrupt-cells: specifies the number of cells needed to encode an
|
|
interrupt source. The value must be 1.
|
|
- compatible: Should contain "rockchip,rk3399-pcie"
|
|
- reg: Two register ranges as listed in the reg-names property
|
|
- reg-names: Must include the following names
|
|
- "axi-base"
|
|
- "apb-base"
|
|
- clocks: Must contain an entry for each entry in clock-names.
|
|
See ../clocks/clock-bindings.txt for details.
|
|
- clock-names: Must include the following entries:
|
|
- "aclk"
|
|
- "aclk-perf"
|
|
- "hclk"
|
|
- "pm"
|
|
- msi-map: Maps a Requester ID to an MSI controller and associated
|
|
msi-specifier data. See ./pci-msi.txt
|
|
- interrupts: Three interrupt entries must be specified.
|
|
- interrupt-names: Must include the following names
|
|
- "sys"
|
|
- "legacy"
|
|
- "client"
|
|
- resets: Must contain seven entries for each entry in reset-names.
|
|
See ../reset/reset.txt for details.
|
|
- reset-names: Must include the following names
|
|
- "core"
|
|
- "mgmt"
|
|
- "mgmt-sticky"
|
|
- "pipe"
|
|
- "pm"
|
|
- "aclk"
|
|
- "pclk"
|
|
- pinctrl-names : The pin control state names
|
|
- pinctrl-0: The "default" pinctrl state
|
|
- #interrupt-cells: specifies the number of cells needed to encode an
|
|
interrupt source. The value must be 1.
|
|
- interrupt-map-mask and interrupt-map: standard PCI properties
|
|
|
|
Required properties for legacy PHY model (deprecated):
|
|
- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
|
|
- phy-names: MUST be "pcie-phy".
|
|
|
|
Required properties for per-lane PHY model (preferred):
|
|
- phys: Must contain an phandle to a PHY for each entry in phy-names.
|
|
- phy-names: Must include 4 entries for all 4 lanes even if some of
|
|
them won't be used for your cases. Entries are of the form "pcie-phy-N":
|
|
where N ranges from 0 to 3.
|
|
(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
|
|
for changing the #phy-cells of phy node to support it)
|
|
|
|
Optional Property:
|
|
- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
|
|
using 24MHz OSC for RC's PHY.
|
|
- ep-gpios: contain the entry for pre-reset GPIO
|
|
- num-lanes: number of lanes to use
|
|
- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
|
|
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
|
|
- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
|
|
- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
|
|
|
|
*Interrupt controller child node*
|
|
The core controller provides a single interrupt for legacy INTx. The PCIe node
|
|
should contain an interrupt controller node as a target for the PCI
|
|
'interrupt-map' property. This node represents the domain at which the four
|
|
INTx interrupts are decoded and routed.
|
|
|
|
|
|
Required properties for Interrupt controller child node:
|
|
- interrupt-controller: identifies the node as an interrupt controller
|
|
- #address-cells: specifies the number of cells needed to encode an
|
|
address. The value must be 0.
|
|
- #interrupt-cells: specifies the number of cells needed to encode an
|
|
interrupt source. The value must be 1.
|
|
|
|
Example:
|
|
|
|
pcie0: pcie@f8000000 {
|
|
compatible = "rockchip,rk3399-pcie";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
|
|
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
|
|
clock-names = "aclk", "aclk-perf",
|
|
"hclk", "pm";
|
|
bus-range = <0x0 0x1>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "sys", "legacy", "client";
|
|
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
|
|
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
|
|
assigned-clock-rates = <100000000>;
|
|
ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
|
|
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
|
|
0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
|
|
num-lanes = <4>;
|
|
msi-map = <0x0 &its 0x0 0x1000>;
|
|
reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
|
|
reg-names = "axi-base", "apb-base";
|
|
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
|
|
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
|
|
<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
|
|
reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
|
|
"pm", "pclk", "aclk";
|
|
/* deprecated legacy PHY model */
|
|
phys = <&pcie_phy>;
|
|
phy-names = "pcie-phy";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pcie_clkreq>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
|
|
<0 0 0 2 &pcie0_intc 1>,
|
|
<0 0 0 3 &pcie0_intc 2>,
|
|
<0 0 0 4 &pcie0_intc 3>;
|
|
pcie0_intc: interrupt-controller {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
};
|
|
|
|
pcie0: pcie@f8000000 {
|
|
...
|
|
|
|
/* preferred per-lane PHY model */
|
|
phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
|
|
phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
|
|
|
|
...
|
|
};
|