69 lines
2.1 KiB
Plaintext
Executable file
69 lines
2.1 KiB
Plaintext
Executable file
* AppliedMicro X-Gene v1 PCIe MSI controller
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Required properties:
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- compatible: should be "apm,xgene1-msi" to identify
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X-Gene v1 PCIe MSI controller block.
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- msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
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- reg: physical base address (0x79000000) and length (0x900000) for controller
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registers. These registers include the MSI termination address and data
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registers as well as the MSI interrupt status registers.
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- reg-names: not required
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- interrupts: A list of 16 interrupt outputs of the controller, starting from
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interrupt number 0x10 to 0x1f.
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- interrupt-names: not required
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Each PCIe node needs to have property msi-parent that points to an MSI
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controller node
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Examples:
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SoC DTSI:
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+ MSI node:
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msi@79000000 {
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compatible = "apm,xgene1-msi";
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msi-controller;
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reg = <0x00 0x79000000 0x0 0x900000>;
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interrupts = <0x0 0x10 0x4>
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<0x0 0x11 0x4>
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<0x0 0x12 0x4>
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<0x0 0x13 0x4>
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<0x0 0x14 0x4>
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<0x0 0x15 0x4>
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<0x0 0x16 0x4>
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<0x0 0x17 0x4>
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<0x0 0x18 0x4>
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<0x0 0x19 0x4>
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<0x0 0x1a 0x4>
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<0x0 0x1b 0x4>
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<0x0 0x1c 0x4>
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<0x0 0x1d 0x4>
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<0x0 0x1e 0x4>
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<0x0 0x1f 0x4>;
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};
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+ PCIe controller node with msi-parent property pointing to MSI node:
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pcie0: pcie@1f2b0000 {
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device_type = "pci";
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compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
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0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
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reg-names = "csr", "cfg";
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ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
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0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
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dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
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0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
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0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
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0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
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0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
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dma-coherent;
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clocks = <&pcie0clk 0>;
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msi-parent= <&msi>;
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};
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