100 lines
4.8 KiB
Plaintext
Executable file
100 lines
4.8 KiB
Plaintext
Executable file
* Marvell Armada XP SoC pinctrl driver for mpp
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Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
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part and usage.
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Required properties:
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- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
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"marvell,mv78460-pinctrl"
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- reg: register specifier of MPP registers
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This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
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Available mpp pins/groups and functions:
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Note: brackets (x) are not part of the mpp name for marvell,function and given
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only for more detailed description in this document.
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* Marvell Armada XP (all variants)
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name pins functions
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================================================================================
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mpp0 0 gpio, ge0(txclkout), lcd(d0)
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mpp1 1 gpio, ge0(txd0), lcd(d1)
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mpp2 2 gpio, ge0(txd1), lcd(d2)
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mpp3 3 gpio, ge0(txd2), lcd(d3)
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mpp4 4 gpio, ge0(txd3), lcd(d4)
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mpp5 5 gpio, ge0(txctl), lcd(d5)
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mpp6 6 gpio, ge0(rxd0), lcd(d6)
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mpp7 7 gpio, ge0(rxd1), lcd(d7)
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mpp8 8 gpio, ge0(rxd2), lcd(d8)
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mpp9 9 gpio, ge0(rxd3), lcd(d9)
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mpp10 10 gpio, ge0(rxctl), lcd(d10)
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mpp11 11 gpio, ge0(rxclk), lcd(d11)
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mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12)
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mpp13 13 gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13)
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mpp14 14 gpio, ge0(txd6), ge1(txd1), spi1(sck), lcd(d15)
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mpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16)
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mpp16 16 gpio, ge0(txd7), ge1(txd3), spi1(cs0), lcd(d16)
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mpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17)
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mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
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mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
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mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
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mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), dram(bat)
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mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
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mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
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mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst)
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mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk)
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mpp26 26 gpio, lcd(clk), tdm(fsync)
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mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
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mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
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mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
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mpp30 30 gpio, tdm(int1), sd0(clk)
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mpp31 31 gpio, tdm(int2), sd0(cmd)
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mpp32 32 gpio, tdm(int3), sd0(d0)
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mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl)
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mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr)
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mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt)
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mpp36 36 gpio, spi0(mosi)
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mpp37 37 gpio, spi0(miso)
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mpp38 38 gpio, spi0(sck)
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mpp39 39 gpio, spi0(cs0)
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mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0),
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spi1(cs1)
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mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
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pcie(clkreq1), spi1(cs2)
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mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer)
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mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout),
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spi1(cs3)
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mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2),
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dram(bat), spi1(cs4)
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mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt),
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spi1(cs5), dram(vttctrl)
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mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt),
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spi1(cs6)
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mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3),
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ref(clkout), spi1(cs7)
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mpp48 48 gpio, dev(clkout), dev(burst/last), nand(rb)
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* Marvell Armada XP (mv78260 and mv78460 only)
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name pins functions
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================================================================================
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mpp49 49 gpio, dev(we3)
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mpp50 50 gpio, dev(we2)
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mpp51 51 gpio, dev(ad16)
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mpp52 52 gpio, dev(ad17)
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mpp53 53 gpio, dev(ad18)
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mpp54 54 gpio, dev(ad19)
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mpp55 55 gpio, dev(ad20)
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mpp56 56 gpio, dev(ad21)
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mpp57 57 gpio, dev(ad22)
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mpp58 58 gpio, dev(ad23)
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mpp59 59 gpio, dev(ad24)
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mpp60 60 gpio, dev(ad25)
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mpp61 61 gpio, dev(ad26)
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mpp62 62 gpio, dev(ad27)
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mpp63 63 gpio, dev(ad28)
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mpp64 64 gpio, dev(ad29)
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mpp65 65 gpio, dev(ad30)
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mpp66 66 gpio, dev(ad31)
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