60 lines
1.6 KiB
Plaintext
Executable file
60 lines
1.6 KiB
Plaintext
Executable file
Device tree binding for NVIDIA Tegra DPAUX pad controller
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========================================================
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The Tegra Display Port Auxiliary (DPAUX) pad controller manages two pins
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which can be assigned to either the DPAUX channel or to an I2C
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controller.
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This document defines the device-specific binding for the DPAUX pad
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controller. Refer to pinctrl-bindings.txt in this directory for generic
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information about pin controller device tree bindings. Please refer to
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the binding document ../display/tegra/nvidia,tegra20-host1x.txt for more
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details on the DPAUX binding.
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Pin muxing:
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-----------
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Child nodes contain the pinmux configurations following the conventions
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from the pinctrl-bindings.txt document.
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Since only three configurations are possible, only three child nodes are
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needed to describe the pin mux'ing options for the DPAUX pads.
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Furthermore, given that the pad functions are only applicable to a
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single set of pads, the child nodes only need to describe the pad group
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the functions are being applied to rather than the individual pads.
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Required properties:
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- groups: Must be "dpaux-io"
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- function: Must be either "aux", "i2c" or "off".
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Example:
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--------
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dpaux@545c0000 {
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...
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state_dpaux_aux: pinmux-aux {
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groups = "dpaux-io";
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function = "aux";
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};
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state_dpaux_i2c: pinmux-i2c {
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groups = "dpaux-io";
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function = "i2c";
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};
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state_dpaux_off: pinmux-off {
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groups = "dpaux-io";
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function = "off";
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};
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};
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...
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i2c@7000d100 {
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...
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pinctrl-0 = <&state_dpaux_i2c>;
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pinctrl-1 = <&state_dpaux_off>;
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pinctrl-names = "default", "idle";
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};
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