144 lines
6.1 KiB
Plaintext
Executable file
144 lines
6.1 KiB
Plaintext
Executable file
NVIDIA Tegra20 pinmux controller
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Required properties:
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- compatible: "nvidia,tegra20-pinmux"
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- reg: Should contain the register physical address and length for each of
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the tri-state, mux, pull-up/down, and pad control register sets.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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Tegra's pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, tristate, drive strength, etc.
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function or tristate parameter. For this
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reason, even seemingly boolean values are actually tristates in this binding:
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unspecified, off, or on. Unspecified is represented as an absent property,
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and off/on are represented as integer values 0 and 1.
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Required subnode-properties:
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- nvidia,pins : An array of strings. Each string contains the name of a pin or
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group. Valid values for these names are listed below.
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Optional subnode-properties:
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- nvidia,function: A string containing the name of the function to mux to the
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pin or group. Valid values for function names are listed below. See the Tegra
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TRM to determine which are valid for each pin or group.
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- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
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0: none, 1: down, 2: up.
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- nvidia,tristate: Integer.
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0: drive, 1: tristate.
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- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
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0: no, 1: yes.
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- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
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0: no, 1: yes.
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- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
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most power. Controls the drive power or current. See "Low Power Mode"
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or "LPMD1" and "LPMD0" in the Tegra TRM.
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- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
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The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
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Tegra TRM.
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- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
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The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
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Tegra TRM.
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- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
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fastest. The range of valid values depends on the pingroup. See
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"DRVDN_SLWR" in the Tegra TRM.
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- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
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fastest. The range of valid values depends on the pingroup. See
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"DRVUP_SLWF" in the Tegra TRM.
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Note that many of these properties are only valid for certain specific pins
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or groups. See the Tegra TRM and various pinmux spreadsheets for complete
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details regarding which groups support which functionality. The Linux pinctrl
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driver may also be a useful reference, since it consolidates, disambiguates,
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and corrects data from all those sources.
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Valid values for pin and group names are:
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mux groups:
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These all support nvidia,function, nvidia,tristate, and many support
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nvidia,pull.
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ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
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ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
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gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
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ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
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ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
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lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
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owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
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spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
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uca, ucb, uda.
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tristate groups:
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These only support nvidia,pull.
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ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
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ld19_18, ld21_20, ld23_22.
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drive groups:
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With some exceptions, these support nvidia,high-speed-mode,
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nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
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nvidia,pull-up-strength, nvidia,slew-rate-rising, nvidia,slew-rate-falling.
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drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
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drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
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drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
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drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
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drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
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drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
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drive_uda.
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Valid values for nvidia,functions are:
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ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4, dap5,
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displaya, displayb, emc_test0_dll, emc_test1_dll, gmi, gmi_int,
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hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio, mipi_hs, nand,
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osc, owr, pcie, plla_out, pllc_out1, pllm_out1, pllp_out2, pllp_out3,
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pllp_out4, pwm, pwr_intr, pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck,
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sdio1, sdio2, sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt,
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spi3, spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi,
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vi, vi_sensor_clk, xio
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Example:
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pinctrl@70000000 {
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compatible = "nvidia,tegra20-pinmux";
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reg = < 0x70000014 0x10 /* Tri-state registers */
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0x70000080 0x20 /* Mux registers */
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0x700000a0 0x14 /* Pull-up/down registers */
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0x70000868 0xa8 >; /* Pad control registers */
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};
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Example board file extract:
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pinctrl@70000000 {
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sdio4_default: sdio4_default {
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atb {
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nvidia,pins = "atb", "gma", "gme";
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nvidia,function = "sdio4";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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};
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};
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sdhci@c8000600 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdio4_default>;
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};
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