154 lines
4.7 KiB
Plaintext
Executable file
154 lines
4.7 KiB
Plaintext
Executable file
* Mediatek MT65XX Pin Controller
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The Mediatek's Pin controller is used to control SoC pins.
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Required properties:
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- compatible: value should be one of the following.
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"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
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"mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
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"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
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"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
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"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
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"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
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"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
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- pins-are-numbered: Specify the subnodes are using numbered pinmux to
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specify pins.
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- gpio-controller : Marks the device node as a gpio controller.
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- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
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binding is used, the amount of cells must be specified as 2. See the below
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mentioned gpio binding representation for description of particular cells.
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Eg: <&pio 6 0>
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<[phandle of the gpio controller node]
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[line number within the gpio controller]
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[flags]>
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Values for gpio specifier:
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- Line number: is a value between 0 to 202.
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- Flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
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Only the following flags are supported:
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0 - GPIO_ACTIVE_HIGH
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1 - GPIO_ACTIVE_LOW
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Optional properties:
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- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
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- reg: physicall address base for EINT registers
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- interrupt-controller: Marks the device node as an interrupt controller
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- #interrupt-cells: Should be two.
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- interrupts : The interrupt outputs from the controller.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices.
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Subnode format
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A pinctrl node should contain at least one subnodes representing the
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pinctrl groups available on the machine. Each subnode will list the
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pins it needs, and how they should be configured, with regard to muxer
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configuration, pullups, drive strength, input enable/disable and input schmitt.
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node {
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pinmux = <PIN_NUMBER_PINMUX>;
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GENERIC_PINCONFIG;
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};
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Required properties:
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- pinmux: integer array, represents gpio pin number and mux setting.
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Supported pin number and mux varies for different SoCs, and are defined
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as macros in boot/dts/<soc>-pinfunc.h directly.
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Optional properties:
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- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
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bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
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input-schmitt-enable, input-schmitt-disable and drive-strength are valid.
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Some special pins have extra pull up strength, there are R0 and R1 pull-up
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resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11.
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So when config bias-pull-up, it support arguments for those special pins.
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Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00.
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See dt-bindings/pinctrl/mt65xx.h.
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When config drive-strength, it can support some arguments, such as
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MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
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Examples:
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#include "mt8135-pinfunc.h"
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...
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{
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syscfg_pctl_a: syscfg-pctl-a@10005000 {
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compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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syscfg_pctl_b: syscfg-pctl-b@1020c020 {
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compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
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reg = <0 0x1020C020 0 0x1000>;
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};
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pinctrl@1c20800 {
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compatible = "mediatek,mt8135-pinctrl";
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reg = <0 0x1000B000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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i2c0_pins_a: i2c0@0 {
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pins1 {
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pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
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<MT8135_PIN_101_SCL0__FUNC_SCL0>;
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bias-disable;
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};
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};
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i2c1_pins_a: i2c1@0 {
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pins {
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pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
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<MT8135_PIN_196_SCL1__FUNC_SCL1>;
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bias-pull-up = <55>;
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};
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};
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i2c2_pins_a: i2c2@0 {
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pins1 {
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pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
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bias-pull-down;
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};
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pins2 {
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pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
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bias-pull-up;
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};
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};
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i2c3_pins_a: i2c3@0 {
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pins1 {
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pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
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<MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
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bias-pull-up = <55>;
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};
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pins2 {
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pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
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<MT8135_PIN_36_SDA3__FUNC_SDA3>;
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output-low;
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bias-pull-up = <55>;
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};
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pins3 {
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pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
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<MT8135_PIN_60_JTDI__FUNC_JTDI>;
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drive-strength = <32>;
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};
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};
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...
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}
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};
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