64 lines
2.4 KiB
Plaintext
Executable file
64 lines
2.4 KiB
Plaintext
Executable file
* FSL MPIC Message Registers
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This binding specifies what properties must be available in the device tree
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representation of the message register blocks found in some FSL MPIC
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implementations.
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Required properties:
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- compatible: Specifies the compatibility list for the message register
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block. The type shall be <string-list> and the value shall be of the form
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"fsl,mpic-v<version>-msgr", where <version> is the version number of
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the MPIC containing the message registers.
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- reg: Specifies the base physical address(s) and size(s) of the
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message register block's addressable register space. The type shall be
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<prop-encoded-array>.
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- interrupts: Specifies a list of interrupt-specifiers which are available
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for receiving interrupts. Interrupt-specifier consists of two cells: first
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cell is interrupt-number and second cell is level-sense. The type shall be
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<prop-encoded-array>.
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Optional properties:
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- mpic-msgr-receive-mask: Specifies what registers in the containing block
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are allowed to receive interrupts. The value is a bit mask where a set
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bit at bit 'n' indicates that message register 'n' can receive interrupts.
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Note that "bit 'n'" is numbered from LSB for PPC hardware. The type shall
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be <u32>. If not present, then all of the message registers in the block
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are available.
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Aliases:
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An alias should be created for every message register block. They are not
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required, though. However, a particular implementation of this binding
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may require aliases to be present. Aliases are of the form
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'mpic-msgr-block<n>', where <n> is an integer specifying the block's number.
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Numbers shall start at 0.
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Example:
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aliases {
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mpic-msgr-block0 = &mpic_msgr_block0;
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mpic-msgr-block1 = &mpic_msgr_block1;
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};
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mpic_msgr_block0: mpic-msgr-block@41400 {
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compatible = "fsl,mpic-v3.1-msgr";
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reg = <0x41400 0x200>;
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// Message registers 0 and 2 in this block can receive interrupts on
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// sources 0xb0 and 0xb2, respectively.
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interrupts = <0xb0 2 0xb2 2>;
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mpic-msgr-receive-mask = <0x5>;
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};
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mpic_msgr_block1: mpic-msgr-block@42400 {
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compatible = "fsl,mpic-v3.1-msgr";
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reg = <0x42400 0x200>;
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// Message registers 0 and 2 in this block can receive interrupts on
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// sources 0xb4 and 0xb6, respectively.
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interrupts = <0xb4 2 0xb6 2>;
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mpic-msgr-receive-mask = <0x5>;
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};
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